News Column

Patent Issued for Data Processing Device

March 4, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent by the inventors Yamada, Kazuo (Kanagawa, JP); Naito, Takao (Kanagawa, JP), filed on December 8, 2010, was published online on February 18, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8656140 is assigned to Fuji Xerox Co., Ltd. (Tokyo, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention relates to a data processing device.

"Reconfigurable circuits (also called programmable logic circuits) of a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array), etc., whose internal logic circuit configuration can be reconfigured (changed) become widespread. Generally, the internal logic circuit configuration of the PLD or the FPGA is set at the circuit starting time, but a device whose logic circuit configuration can be changed during the operation of the circuit is also developed. In recent years, use of a dynamically reconfigurable processor (DRP) whose internal logic circuit configuration can be reconfigured at high speed (for example, in one clock cycle) has also advanced.

"The logic circuit configuration reconfigured on a reconfigurable circuit is called configuration. In a system using a reconfigurable circuit, generally, the configuration of the reconfigurable circuit is rewritten in order, whereby a circuit of a scale that cannot be configured on the reconfigurable circuit at a time can be implemented using the reconfigurable circuit.

"In the system using the reconfigurable circuit, generally the reconfigurable circuit is often used under the control of a general-purpose CPU. A combination of software processing of a part of a processing sequence by a CPU and hardware processing of another part by a reconfigurable circuit is often conducted. Hitherto, in such a system, generally each of the CPU and the reconfigurable circuit has been provided with dedicated memory and data being processed by each of the CPU and the reconfigurable circuit has been read from and written to their respective memories.

"In contrast to the conventional implementation system, it is considered that work memory of the CPU and the reconfigurable circuit is made common, whereby the memory cost is reduced and device is installed in an existing ASCI, etc., as IP core, whereby the device cost is reduced and the board occupation area is also decreased. In this case, however, it is necessary to note the relationship among bandwidths of the CPU, the reconfigurable circuit, and the memory. For example, to use the reconfigurable circuit (particularly, DRP) for image processing such as processing of a bit map image in print, handled image data is large and thus the input/output bandwidth of the reconfigurable circuit occupies the memory bandwidth and the memory band assigned to the CPU (and its peripheral devices) cannot be assigned.

"In contrast, for example, it is also considered that an internal buffer of a small capacity is created on a chip on which a reconfigurable circuit is mounted and the processing result of the configuration formed on the reconfigurable circuit is passed to the next configuration through the internal buffer, whereby the memory band used by the reconfigurable circuit is decreased. To use the internal buffer of the small capacity, the data to be processed needs to be separated for each amount responsive to the capacity of the buffer for processing. In window processing of reading data of one window width with one data point (for example, pixel) as the reference to calculate the data point, for example, like filtering of an image, it is necessary to read extra data as much as the window width at both ends of the range of the data to be processed. Thus, to separate the data to be processed in a comparatively small amount at a time and read the data into the internal buffer, the relative rate of the window width to the amount of the data to be processed becomes high, resulting in degradation of the processing performance (processing efficiency). For example, filtering using a filter of 11.times.11 pixels is applied to a 33-line image read from the internal buffer, only 23-line image is obtained as the processing result and the processing efficiency becomes 23/33=about 70%."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "According to an aspect of the invention, a data processing device includes a reconfigurable circuit, a reconfiguration unit, an internal memory, a connection circuit, a selection unit and a selection control unit. The reconfigurable circuit includes a plurality of configurations. The reconfiguration unit reconfigures the plurality of configurations in order so as to configure a pipeline. The connection circuit connects to an external memory in an external device. The selection unit selects connection destinations for data input and data output of each of the configurations reconfigured on the reconfigurable circuit from between the internal memory and the external memory via the connection circuit. In a first data transfer manner, data to be processed is input to a top configuration in the pipeline without the data being divided, each configuration in the pipeline are processed, and a processing result of each configuration is transferred to the next configuration in the pipeline through the external memory. In a second data transfer manner, the data to be processed is divided into data units of the data amount responsive to the capacity of the internal memory and is input to a top configuration in the pipeline, each configuration in the pipeline are processed, and a processing result of each configuration is transferred to the next configuration in the pipeline through the internal memory. The selection control unit (i) calculates a bandwidth of the pipeline based on the data input/output to/from the external memory in each of the data transfer manners and a performance index value of the pipeline based on the ratio of the amount of data output from the pipeline to the amount of data input to the pipeline in each of the data transfer manners, (ii) selects one of the data transfer manners based on the bandwidth and the performance index value of each of the data transfer manners, and (iii) controls a selection of the selection unit in accordance with the selected data transfer manner."

URL and more information on this patent, see: Yamada, Kazuo; Naito, Takao. Data Processing Device. U.S. Patent Number 8656140, filed December 8, 2010, and published online on February 18, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=18&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=885&f=G&l=50&co1=AND&d=PTXT&s1=20140218.PD.&OS=ISD/20140218&RS=ISD/20140218

Keywords for this news article include: Fuji Xerox Co. Ltd., Information Technology, Information and Data Processing.

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Source: Information Technology Newsweekly


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