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"Multiport Memory Emulation Using Single-Port Memory Devices" in Patent Application Approval Process

March 4, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Kokrady, Aman A. (Mayur Vihar Phase 1, IN); Ali, Shahid (New Delhi, IN); Visvanathan, Vish (Chennai, IN); Menezes, Vinod Joseph (Bangalore, IN), filed on August 9, 2012, was made available online on February 20, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Texas Instruments, Incorporated.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Electronic devices include a wide variety of processors such as application specific integrated circuits (ASIC), digital signal processors (DSP), and microprocessors that use memory devices to store and retrieve information, for example. Very large scale integration (VLSI) circuits (e.g., on the scale of billions of transistors) often include multiple processors that each access and process information that is stored in memory devices that are shared by the multiple processors. The shared memory devices often include memory cells (e.g., bitcells) having multiple ports (e.g., multiport memories) so that the memory devices (and the information stored therein) can be accessed more quickly.

"However, implementing multiport memories using space and/or time multiplexing typically requires a greater amount a layout space, increased power, decreased bandwidth, and/or combinations thereof. Space-multiplexing multiport memories, for example, are arranged using a multiplexor that is arranged to receive requests for first and second ports and to alternate sending the request to a memory. Time-multiplexing multiport memories, for example, are arranged using first and second memories that are arranged to respectively receive requests for first and second memories and a multiplexor that is arranged to alternate output the output of each of the first and second memories.

"The space-multiplexing approach typically entails using a larger bitcell (e.g., using eight or more-transistors). The (layout) area of each multiport bitcell typically increases exponentially with the number of ports in the bitcell, which results in exponentially greater space requirements for greater numbers of ports in a bitcell. Space-multiplexing typically allows the multiport memory to run at frequencies close to that of a single-port memory. Thus, space-multiplexed memories often use twice the area of, offer similar performance to, and consume twice the power of a single-port memory.

"The time-multiplexing approach includes using single-port memories that are coupled to arbitration and priority sequencing logic to avoid bank contentions. Individual port requests for a single-port memory are prioritized and are sequentially sent in time to the single-port memories. The serialization of the individual port requests results in lower frequencies of operation and higher cycle latencies since the single-port memories are accessed sequentially in time. Multiport memories using time-multiplexing typically have a layout area that is comparable to the size of the layout area of single port. Thus, time-multiplexed memories often use a similar amount of area as, offer half the performance of, and consume a similar amount of the power of a single-port memory.

"A third approach for implementing multiport memories provides using first and second inputs ports as well as using first and second output ports for a single bitcell such as an '8T' (eight-transistor) bitcell. The multiple-input and multiple-output memories often use twice the area of, offer less performance than, and consume more power than a single-port memory."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The problems noted above are solved in large part by a multiport memory emulator that receives a first and a second memory command for concurrent processing of memory commands in one operation clock cycle. Concurrent processing of both read and write commands is supported by a two-level architecture when the command types of the first and second memory commands are both read command types, are both write command types, or are both different command types. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 shows an illustrative computing device in accordance with embodiments of the disclosure;

"FIG. 2 is a logic diagram illustrating a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 3 is a logic diagram illustrating the physical banks of a single-port memory of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 4 is a logic diagram illustrating a lookup table for an logically addressed emulator single-port memory array in accordance with embodiments of the disclosure;

"FIG. 5 is a flow diagram illustrating a process for concurrently accessing two ports of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 6 is a logic diagram illustrating the state of a lookup table of an logically addressed emulator single-port memory array after a first update to the logic table in accordance with embodiments of the disclosure;

"FIG. 7 is a logic diagram illustrating the state of a lookup table of an logically addressed emulator single-port memory array after a second update to the logic table in accordance with embodiments of the disclosure;

"FIG. 8 is a timing diagram that illustrates access cycles of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 9 is a logic diagram illustrating the physical banks and an encoded data bank of a single-port memory of a multiport memory emulator for simultaneously processing parallel read operations from the same bank in accordance with embodiments of the disclosure;

"FIG. 10 is a timing diagram that illustrates the memory operations of FIG. 9 in accordance with embodiments of the disclosure;

"FIG. 11 is a logic diagram illustrating the physical banks and an encoded data bank of a single-port memory of another multiport memory emulator for simultaneously processing parallel read operations from the same bank in accordance with embodiments of the disclosure;

"FIG. 12 is a timing diagram that illustrates the memory operations of FIG. 11 in accordance with embodiments of the disclosure;

"FIG. 13 is a logic diagram illustrating the physical banks and an encoded data bank of a single-port memory of another multiport memory emulator for simultaneously processing parallel read operations from the same bank in accordance with embodiments of the disclosure;

"FIG. 14 is a timing diagram that illustrates the memory operations of FIG. 13 in accordance with embodiments of the disclosure;

"FIG. 15 is a flow diagram illustrating a process for concurrently reading two ports of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 16 is a logic diagram that illustrates a full dual read and write architecture multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 17 is a logic diagram illustrating a lookup table 1700 for a level-two logically addressed emulator single-port memory in accordance with embodiments of the disclosure;

"FIG. 18 is a logic diagram that illustrates simultaneous read operations in a full dual read and write architecture multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 19 is a logic diagram that illustrates simultaneous write operations in a full dual read and write architecture multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 20 is a flow diagram illustrating a process for concurrently reading and writing two ports of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure;

"FIG. 21 is a flow diagram illustrating a process for concurrently reading two ports of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure; and

"FIG. 22 is a flow diagram illustrating a process for concurrently writing two ports of a logically addressed multiport memory emulator in accordance with embodiments of the disclosure."

URL and more information on this patent application, see: Kokrady, Aman A.; Ali, Shahid; Visvanathan, Vish; Menezes, Vinod Joseph. Multiport Memory Emulation Using Single-Port Memory Devices. Filed August 9, 2012 and posted February 20, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=415&p=9&f=G&l=50&d=PG01&S1=20140213.PD.&OS=PD/20140213&RS=PD/20140213

Keywords for this news article include: Legal Issues, Information Technology, Texas Instruments Incorporated, Information and Data Aggregation.

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Source: Information Technology Newsweekly


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