The assignee for this patent application is Universite Francois Rabelais.
Reporters obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to the field of electronic chips. It more specifically aims at surface mount (or flip-chip) chips, that is, chips comprising, on the side of at least one surface, electric connection pads intended to be directly soldered to contact areas of an external device such as a printed circuit board or another chip.
"FIGS. 1A and 1B schematically show a surface mount chip 100. FIG. 1A is a top view, and FIG. 1B is a cross-section view along plane B-B of FIG. 1A. Chip 100 comprises a substrate 101, for example, a semiconductor substrate, inside and on top of which are formed one or several electronic components (not shown). On one side of a surface (the upper surface in the shown example,), chip 100 comprises electric connection pads 103 (four pads in the present example) intended to be directly soldered to contact areas of an external device (not shown). Each pad 103 comprises a metallization 105, for example, having a circular shape (in top view), and a connection element 107 such as a solder bump or a solidified solder drop, coating metallization 105.
"When assembled in an external device, the chip is positioned so that connection elements 107 bear against corresponding contact areas of the external device. The assembly is then heated beyond the melting point of connection elements 107 to perform the soldering.
"Some flip-chip assembled chips, for example, some discrete component chips or some microbattery chips, only comprise two pads of electric connection on the side of their surface of connection to an external device.
"FIGS. 2A to 2C schematically show a surface mount chip 200 only comprising two electric connection pads 203 on the side of its surface of connection to an external device (upper surface in the shown example). FIG. 2A is a top view, and FIGS. 2B and 2C are cross-section views, respectively along planes B-B and C-C of FIG. 2A.
"For mechanical stability reasons, pads 203 are not point-shaped pads of the type described in relation with FIG. 1, but have an elongated shape (in top view). Each of pads 203 comprises a metallization 205 of elongated shape, formed on the upper surface side of substrate 101, and an elongated connection element 207 coating metallization 205. As an example, metallization 205 comprises two circular lands connected by a conductive strip, and connection element 207 is formed from two solder bumps or two drops of solder paste respectively arranged on the two circular lands. After anneal, the solder material spreads on the entire surface of metallization 205, and connection element 207 takes an elongated shape comprising a substantially rectilinear upper edge.
"In the shown example, chip 200 has, in top view, a generally rectangular shape. Pads 203 are arranged parallel to the shortest chip edges, respectively close to the two opposite short chip edges. The length of pads 203 is of the same order of magnitude as the length of the short chip edges.
"Chip 200 of FIG. 2 has the advantage of being able to be in a position of equilibrium on its connection pads 203 when flipped, which makes its assembly in an external device easier. It should in particular be noted that if pads 203 were point-shaped pads of the type described in relation with FIG. 1, the chip could not be stable on two pads only. This would make chip-assembly handling operations in an external device particularly delicate. This would further result in a relatively fragile assembly, and thus in an unreliable final device.
"The use of elongated pads, however, has the disadvantage that the pads take up, in top view, a surface area greater than that taken up by point-shaped pads of the type described in relation with FIG. 1. This all the more decreases the substrate surface area available to form components. This further increases stray capacitances between the pads and the substrate."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "An embodiment provides a surface mount chip only comprising two contact pads on the side of a surface of connection to an external device, this chip at least partly overcoming some of the disadvantages of existing chips.
"Thus, an embodiment provides a surface mount chip comprising, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad.
"According to an embodiment, in top view, the largest dimension of the first pad is greater by at least a factor 2 than that of the second pad.
"According to an embodiment, the chip has, in top view, a rectangular general shape.
"According to an embodiment, the first pad is substantially parallel to the two shortest chip edges.
"According to an embodiment, the second pad is approximately equidistant from the two longest chip edges.
"According to an embodiment, in top view, the largest dimension of the first pad is at least equal to half the smallest width of the chip.
"According to an embodiment, in top view, the largest dimension of the second pad is smaller than 10 percent of the smallest width of the chip.
"According to an embodiment, in top view, the smallest width of the rectangle circumscribed in the first pad is substantially equal to the largest dimension of the second pad.
"According to an embodiment, the first pad comprises two conductive bumps or drops interconnected by a conductive strip.
"According to an embodiment, the second pad comprises a conductive bump or drop.
"The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIGS. 1A and 1B, previously described, are top and cross-section views schematically showing an example of a surface mount chip;
"FIGS. 2A to 2C, previously described, are top and cross-section views schematically showing another example of a surface mount chip;
"FIG. 3 is a top view schematically showing an embodiment of a surface mount chip;
"FIG. 4 is a top view schematically showing an alternative embodiment of a surface mount chip; and
"FIGS. 5A to 5C are top and cross-section views schematically showing another alternative embodiment of a surface mount chip.
"For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of electronic chips, the various drawings are not to scale."
For more information, see this patent application: Ory, Olivier;
Keywords for this news article include: Universite Francois Rabelais.
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