News Column

Patent Application Titled "Power on Reset Generation Circuits in Integrated Circuits" Published Online

February 27, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Shrivastava, Aatmesh (Richardson, TX); Yadav, Rajesh (Bangalore, IN), filed on August 6, 2012, was made available online on February 13, 2014.

The assignee for this patent application is Texas Instruments Incorporated.

Reporters obtained the following quote from the background information supplied by the inventors: "A number of integrated circuits, such as SoCs, include a variety of electronic devices that are electrically (or electronically) interconnected (or communicatively associated or coupled with one another). Some examples of such devices include, but are not limited to, memory devices, flip-flops, latches, registers and counters, and these devices hold signals in the form of binary levels such as logic '0' and logic '1'. In order to operate in real world applications, an exemplary implementation provides that such devices are to be in a known state, such as, for example, in a logic '1' state or a logic '0' state.

"In certain exemplary applications, a power on reset (POR) pulse is used to pre-set, or pre-reset, these devices (such as the memory devices, flip-flops, latches and registers and counters). The POR pulse is generated on-chip so as to reduce cost and achieve better performance as compared to the exemplary scenario where the POR pulse is generated external to the chip, as the POR generated on-chip tends to be free, or relatively free, from inter-module and inter-chip noise. It is noted, however, that reducing the area and complexity of on-chip circuits that are configured to generate the POR pulse may be challenging."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "A number of exemplary Integrated Circuit (ICs), including circuits configured to generate a power on reset (POR) pulse, are disclosed. In an embodiment, an IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level. The IC also comprises a pulse generation circuit communicatively associated or coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit communicatively associated or coupled with the pulse generation circuit. The reset generation circuit is configured to (1) receive the POR pulse and (2) generate a reset pulse based on the POR signal and of at least one control signal, wherein the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

"In some embodiments, a number of exemplary circuits configured to sense a power supply in a number of ICs are disclosed. In an embodiment, a circuit configured to sense the power supply comprises a voltage divider circuit comprising a first resistor and a second resistor coupled or positioned between a power supply and a reference supply. The voltage divider circuit is configured to generate a first signal proportional to the power supply signal at a node between the first resistor and the second resistor. The circuit also includes a Metal Oxide Semiconductor (MOS) transistor having first, second and third terminals, wherein the first terminal is communicatively associated or coupled with the node that is positioned to receive the first signal, the second terminal is communicatively associated or coupled with the power supply, and the third terminal is communicatively associated or coupled with the reference supply through a resistor. The MOS transistor is configured to assert or transmit a second signal at the third terminal upon, or in response to, the first signal being greater than a threshold voltage.

"In one embodiment, the circuit configured to sense the power supply further comprises an inverter circuit comprising at least one PMOS transistor and at least one NMOS transistor coupled or positioned between the power supply and the reference supply. The inverter circuit is configured to (1) receive the second signal at gate terminals of the at least one PMOS transistor and the at least one NMOS transistor and (2) generate the sense signal at an output terminal of the inverter circuit in response to the second signal and the power supply signal. The sense signal follows (is substantially equal to) the power supply signal when the power supply signal ramps from the first level to a threshold level, wherein the threshold level is a level between the first level and the second level, and the sense signal transitions from the threshold level to the first level upon assertion or transmission of the second signal.

"In some embodiments, a number of exemplary pulse generation circuits configured to generate a power on reset (POR) pulse in response to a sense signal (representing an 'ON' state of a power supply in an IC) are disclosed. A pulse generation circuit comprises one or more delay blocks connected or coupled in a serial configuration such that the one or more delay blocks are positioned to generate the POR pulse. Each delay block comprises an inverter configured by a NMOS transistor and a PMOS transistor, wherein the inverter is configured to receive an input signal and provide an inverted input signal at an output terminal of the inverter. The delay block further comprises a MOS based resistor having a first node and a second node, wherein the first node is communicatively associated or coupled with the output of the inverter so as to be positioned to receive the inverted input signal and pass or transmit the inverted input signal to the second node. The delay block further comprises an amplifier circuit (e.g., a Miller amplifier) comprising an inverting voltage amplifier and a miller capacitor coupled or positioned between an input node and an output node of the inverting voltage amplifier, wherein the charging and discharging of an equivalent capacitor at the input node of the inverting voltage amplifier is configured to generate a pulse of a pre-determined width or duration at the output node of the amplifier.

"In an embodiment, the delay block further comprises a Schmitt trigger buffer communicatively associated or coupled with the output node of the inverting voltage amplifier. The trigger buffer is configured to receive the pulse of pre-determined width or duration and provide a portion of the POR pulse at an output node of the Schmitt trigger buffer. The input signal received by the inverter is the sense signal for the first delay block of the serial configuration of the pulse generation circuit. Additionally, the input signal is the output of the trigger buffer of a preceding delay block, which is arranged or positioned in the serial configuration with the remaining delay blocks. The one or more delay blocks are configured to generate the POR pulse of the threshold duration.

BRIEF DESCRIPTION OF THE VIEWS OF THE DRAWINGS

"FIG. 1A is a block diagram of an exemplary integrated circuit (IC) configured to have a reset signal generated thereon in accordance with an embodiment;

"FIG. 1B is an exemplary waveform representation of signals of FIG. 1A;

"FIG. 2 is a circuit diagram of a first exemplary power supply sense circuit of an IC in accordance with an embodiment;

"FIG. 3 is a circuit diagram of a second exemplary power supply sense circuit of an IC in accordance with an embodiment;

"FIG. 4 is a block diagram of an exemplary pulse generation circuit of an IC in accordance with an embodiment;

"FIG. 5 is a circuit diagram of a first exemplary delay block of a pulse generation circuit in accordance with an embodiment;

"FIG. 6 is a circuit diagram of a second exemplary delay block of a pulse generation circuit in accordance with an embodiment;

"FIG. 7 is a timing waveform of the first and second exemplary delay blocks in accordance with an embodiment;

"FIG. 8 is a circuit diagram of a third exemplary delay block of a pulse generation circuit in accordance with an embodiment;

"FIG. 9 is a block diagram representation of an exemplary generation of reset signal based on a POR pulse in an IC in accordance with an embodiment; and

"FIG. 10 is a timing diagram of an exemplary generation of a reset signal in the IC of FIG. 9, in accordance with an embodiment."

For more information, see this patent application: Shrivastava, Aatmesh; Yadav, Rajesh. Power on Reset Generation Circuits in Integrated Circuits. Filed August 6, 2012 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5457&p=110&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Texas Instruments Incorporated.

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Source: Politics & Government Week


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