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Researchers Submit Patent Application, "Storage Method, Memory, and Storing System with Accumulated Write Feature", for Approval

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Jochen, Hoffmann (Xi'an, CN), filed on December 30, 2011, was made available online on February 13, 2014.

The patent's assignee is Xi'an Sinochip Semiconductors Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "Different types of memories, such as dynamic random access memory (DRAM), static random access memory (SRAM), and Flash, have been used in almost all modern electronic devices (e.g., computer, mobile phone, router, set-top box, printer, Global Positioning System (GPS)). These memories can be used to store and retrieve binary data which are processed by a different part of the system (e.g., Central Processing Unit (CPU)).

"For a write operation of a memory, the memory may give an address and a write instruction, and give data upon or after giving the write instruction. The data may be subsequently written to a memory cell of the selected address (depending on the type of the used storage device, data may be transmitted at each single period via a single pin or multiple parallel pins, or data may be transmitted in a burst over multiple periods).

"Data previously stored at the same address may be overwritten unconditionally according to the write instruction.

"For a read operation of the memory, an address and a read instruction may be provided to the memory. After a certain delay (i.e., time required for retrieving data), the memory may output data (transmitting data at each period or in a burst over multiple periods), and a controller or CPU may latch or process the data.

"The memory usually functions as a servant device in the system. That is, the memory executes a given instruction (address and instruction are both unidirectional, i.e., from the controller/CPU to the memory). On the contrary, a data transmission line is bidirectional, i.e., the memory can receive data (at a write operation) and transmit data (at a read operation).

"Data throughput realized with a single memory/multiple memories is a key factor for maximizing the overall speed of a system. Data can flow unidirectionally from the controller to the memory only after a write instruction is executed. The First-in First-out (FIFO) act within the controller can reduce the delay/latency between address/instruction and data. In this way, it is possible to continuously output data over the data transmission line (and thus the maximal data rate may be reached).

"The above principle is also applicable to a sequence containing only read instructions. Data flow unidirectionally from the controller/CPU to the memory. It is possible to reach the maximal data rate with a continuous use of the data transmission line (transmitting a continuous sequence of addresses/instructions, and thus continuously outputting data).

"There will be a considerable decrease in the data rate, if the instruction sequence includes alternately read and write instructions. The reason for such phenomenon is that for each switching from a read instruction to a write instruction, the bidirectional data transmission line has to change its transmission direction, and vice versa. As an example, the controller issues a read instruction. Data appear at the data pin of the memory after a certain delay (i.e., read delay). The data are transmitted to the controller via the data transmission line and received by the controller. At this time, if the next instruction is a write instruction, the controller can transmit data to the memory only after the controller safely receives and stores the data previously sent from the memory. Otherwise, data conflict may occur, and the previously-sent data may be lost. Once the controller allows data transmission, the data will be transmitted from the controller to the memory via the data transmission line, received by the memory, and transferred and stored in the selected cell of the memory. The next read instruction can be executed only after the foregoing operation is completed.

"It is thus desirable to enable a long-term unidirectional transmission on the data transmission line, instead of any switching from read to write (or vice versa) of the data transmission line between the controller/CPU and the memory, thereby reducing the occurrence frequency for such switching of the data transmission line. Unfortunately, the defined operations/algorithms have to utilize a large amount of data (e.g., pattern recognition algorithm, neural network, plotting error, and the like).

"For example, an operation X:=X|Y; (fetch data X; perform OR operation on data Y and X; and store new data X) requires one CPU and one memory in the system, and is executed through the following sequence:

"a) CPU issues a read instruction to the memory to retrieve data X; b) CPU waits so that the read instruction is sent to the memory, and the memory decodes and executes the instruction, and then output data to the data transmission line (i.e., read delay); c) CPU retrieves data X; d) the Arithmetic Logical Unit (ALU) within CPU performs an operation X|Y (assuming that data Y is stored in a register); e) CPU issues a write instruction to write the operation result (X:=X|Y) in the memory; f) depending on the type of the memory (e.g., DDR2, or DDR3 DRAM), CPU waits until the write instruction has been sent, and then transmits data; g) the memory receives the data transmitted via the data transmission line from CPU to the memory, and the data are transferred inside the memory to a corresponding memory cell and stored therein.

"After all the above steps are completed, the memory can then read next piece of data.

"According to the minimal specified timing when multiple read and write instructions are executed in the standard of DDR3 DRAM, the following will be seen:

"a) read operations are performed in a continuous form of read-to-read operations and continuous data output (the data transmission line can be 100% used); b) write-to-write operations can also enable 100% use of the data transmission line; c) a small interval is required for switching from read to write, and is 2 clock cycles (4 cycles of data, 2 cycles of the interval, and thus the utilization of the data transmission line is 66%); d) the worst case for DRAM is switching from write to read, that is, next read can be executed only after data in all memory cells have been read; 13 cycles are required between issuance of a write instruction and issuance of a read instruction (4 cycles of data, 9 cycles of interval, and thus the utilization of the data transmission line is 31%).

"So far, a method for solving the above problems is reducing the switching frequency by read/write larger blocks of data at any time. Another method is adding one or more intermediate cache memories of different levels. The cache memory is a high-speed memory that can read/write larger data blocks from a low-speed memory to a cache line or area. This can reduce the total number of times the low-speed memory is accessed, and also can improve data access efficiency with transmission of data blocks.

"Although the faster cache memory can shorten the delay period, the above method cannot solve each of the foregoing problems when data for OR or AND operation are stored in the cache memory."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "An object of the present invention is to provide a storage method, a memory and a storage system that have an accumulated write feature. With the present invention, the OR operation and the AND operation are shifted from CPU/ALU (controller) to the memory, and the frequency for switching data transmission lines between read and write instructions can be reduced.

"A solution of the present invention is a storage method with an accumulated write feature, comprising:

"1) providing a standard instruction interface between a controller or CPU and a memory, so that the controller or CPU can send a write instruction, an address instruction and a write arithmetic instruction to the memory, wherein the write arithmetic instruction comprises a 'write_OR' instruction and/or a 'write_AND' instruction; 2) decoding the write instruction, the address instruction and the write arithmetic instruction by an instruction/address decoder in the memory; 3) if a 'write_OR' instruction is decoded, turning on a 'write_OR' data switch of complementary data switches in a memory cell corresponding to the address instruction, wherein data written from a data transmission line can switch non-inverted data in cross-coupled inverters from 0 to 1, but not from 1 to 0; if a 'write_AND' instruction is decoded, turning on a 'write_AND' data switch of the complementary data switches in the memory cell corresponding to the address instruction, wherein the data written from the data transmission line can switch the non-inverted data in the cross-coupled inverters from 1 to 0, but not from 0 to 1; if a write instruction is decoded, turning on both of the complementary data switches in the memory cell corresponding to the address instruction, wherein the data written from the data transmission line can switch the data in the cross-coupled inverters in a bidirectional manner.

"The memory cell may comprise SRAM cell, DRAM cell or FLASH cell.

"A first memory with an accumulated write feature comprises an interface unit, an instruction/address decoder, a plurality of memory cells, and data transmission lines comprising a non-inverted data transmission line and an inverted data transmission line, each of the memory cell comprises two complementary data switches and two cross-coupled inverters; each of the inverters comprises a p-type field effect transistor (pFET) and a n-type FET (nFET); the instruction/address decoder has output terminals coupled to the two complementary data switches, respectively; the two complementary data switches are coupled to the non-inverted data transmission line and the non-inverted data, and to the inverted data transmission line and the inverted data, respectively; the memory is characterized by: the interface unit comprises a write arithmetic instruction interface, a write instruction interface, and an address instruction interface; the write arithmetic instruction interface comprises a 'write_OR' instruction interface and/or a 'write_AND' instruction interface; the instruction/address decoder is configured to decode a write arithmetic instruction, a write instruction and an address instruction; the pFET has a higher driving capability than the data switches, and the nFET has a lower driving capability than the data switches.

"The memory cell may comprise SRAM cell, DRAM cell or FLASH cell.

"A second memory with an accumulated write feature comprises an interface unit, an instruction/address decoder, a plurality of memory cells, and data transmission lines comprising a non-inverted data transmission line and a inverted data transmission line, each of the memory cell comprises two complementary data switches and two cross-coupled inverters; each of the inverters comprises a p-type field effect transistor (pFET) and a n-type FET (nFET); the instruction/address decoder has output terminals coupled to the two complementary data switches, respectively; the two complementary data switches are coupled to the non-inverted data transmission line and the non-inverted data, and to the inverted data transmission line and the inverted data, respectively; the memory is characterized by: the interface unit comprises a write arithmetic instruction interface, a write instruction interface, and an address instruction interface; the write arithmetic instruction interface comprises a 'write_OR' instruction interface and/or a 'write_AND' instruction interface; the instruction/address decoder is configured to decode a write arithmetic instruction, a write instruction and an address instruction; the pFET has a lower driving capability than the data switches, and the nFET has a higher driving capability than the data switches.

"The memory cell may comprise SRAM cell, DRAM cell or FLASH cell.

"A first storage system with an accumulated write feature comprises a memory controller or CPU, an instruction/address decoder, data transmission lines, a plurality of caches and a plurality of memory cells, the data transmission lines comprising a non-inverted data transmission line and a inverted data transmission line, each of the memory cell comprises two complementary data switches and two cross-coupled inverters; each of the inverters comprises a p-type field effect transistor (pFET) and a n-type FET (nFET); the instruction/address decoder has output terminals coupled to the two complementary data switches, respectively; the two complementary data switches are coupled to the non-inverted data transmission line and the non-inverted data, and to the inverted data transmission line and the inverted data, respectively; the storage system is characterized by: the controller is configured to issue a write arithmetic instruction, a write instruction and an address instruction to the instruction/address decoder; the write arithmetic instruction comprises a 'write_OR' instruction and/or a 'write_AND' instruction; the instruction/address decoder is configured to decode a write arithmetic instruction, a write instruction and an address instruction; the pFET has a higher driving capability than the data switches, and the nFET has a lower driving capability than the data switches.

"The memory cell may comprise SRAM cell, DRAM cell or FLASH cell.

"A second storage system with an accumulated write feature comprises a memory controller or CPU, an instruction/address decoder, data transmission lines, a plurality of caches and a plurality of memory cells, the data transmission lines comprising a non-inverted data transmission line and a inverted data transmission line, each of the memory cell comprises two complementary data switches and two cross-coupled inverters; each of the inverters comprises a p-type field effect transistor (pFET) and a n-type FET (nFET); the instruction/address decoder has output terminals coupled to the two complementary data switches, respectively; the two complementary data switches are coupled to the non-inverted data transmission line and the non-inverted data, and to the inverted data transmission line and the inverted data, respectively; the storage system is characterized by: the controller is configured to issue a write arithmetic instruction, a write instruction and an address instruction to the instruction/address decoder; the write arithmetic instruction comprises a 'write_OR' instruction and/or a 'write_AND' instruction; the instruction/address decoder is configured to decode a write arithmetic instruction, a write instruction and an address instruction; the pFET has a lower driving capability than the data switches, and the nFET has a higher driving capability than the data switches.

"The memory cell may comprise SRAM cell, DRAM cell or FLASH cell.

"The present invention has the following advantages:

"a) the present invention can reduce the work load of CPU/ALU; b) the present invention can continuously write data to the memory (without first reading data); that is, there is no need for execution of the cycle of read-wait-write-wait, and only a write instruction is executed; in this way, it is now sufficient to access the memory only once, other than twice in the conventional technology; c) the present invention can avoid delay caused by the switching since only the write instructions needs to be executed, and can be executed in a continuous manner.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a typical circuit diagram of a conventional SRAM;

"FIG. 2 is a circuit diagram showing a SRAM that can execute a 'write_OR' instruction according to the present invention;

"FIG. 3 is another circuit diagram showing a SRAM that can execute a 'write_OR' instruction according to the present invention;

"FIG. 4 is a circuit diagram showing a SRAM that can execute a 'write_AND' instruction according to the present invention;

"FIG. 5 is another circuit diagram showing a SRAM that can execute a 'write_AND' instruction according to the present invention;

"FIG. 6 is a circuit diagram showing a SRAM that can execute 'write_OR' and 'write_AND' instructions according to the present invention;

"FIG. 7 is another circuit diagram showing a SRAM that can execute 'write_OR' and 'write_AND' instructions according to the present invention;

"FIG. 8 is a typical circuit diagram of a conventional DRAM;

"FIG. 9 is a circuit diagram showing a DRAM that can execute a 'write_OR' instruction according to the present invention;

"FIG. 10 is another circuit diagram showing a DRAM that can execute a 'write_OR' instruction according to the present invention;

"FIG. 11 is a circuit diagram showing a DRAM that can execute a 'write_AND' instruction according to the present invention;

"FIG. 12 is another circuit diagram showing a DRAM that can execute a 'write_AND' instruction according to the present invention;

"FIG. 13 is a circuit diagram showing a DRAM that can execute 'write_OR' and 'write_AND' instructions according to the present invention;

"FIG. 14 is another circuit diagram showing a DRAM that can execute 'write_OR' and 'write_AND' instructions according to the present invention."

For additional information on this patent application, see: Jochen, Hoffmann. Storage Method, Memory, and Storing System with Accumulated Write Feature. Filed December 30, 2011 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=489&p=10&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Electronics, Data Transmission, Random Access Memory, Xi'an Sinochip Semiconductors Co. Ltd.

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Source: Electronics Newsweekly


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