Researchers Submit Patent Application, "Semiconductor Device Generating Internal Clock Signal Having Higher Frequency than That of Input Clock Signal", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a multiplier oscillator that multiplies a clock signal.
"A ring oscillator is generally known as a circuit that generates an internal clock signal with a high frequency (see Japanese Patent Application Laid-open No. 2010-192976). The ring oscillator includes odd numbers of inverter circuits cyclically-connected to generate a clock signal with a predetermined frequency depending on not only the number of stages of the inverter circuits, but also characteristics of transistors included in the inverter circuits, an operating voltage, and the like. The clock signal generated by the ring oscillator is supplied to, for example, a PLL (
"However, in the PLL circuit using the ring oscillator, a generable frequency of the internal clock signal is limited by the oscillation frequency of the ring oscillator and thus the oscillation frequency of the ring oscillator needs to be increased to generate the internal clock signal with a higher frequency. Accordingly, in some cases, a boosted potential needs to be used as the operating voltage of the ring oscillator, which increases the circuit scale.
"In recent years, the operating voltage of a semiconductor device tends to be lowered from a viewpoint of reducing power consumption or decreasing jitter. Meanwhile, a threshold voltage of a transistor is sometimes designed to be sufficiently high to reduce an off-leakage current of the transistor. A decrease in the operating voltage or an increase in the transistor threshold voltage increases a delay amount of each stage of the inverter circuits included in the ring oscillator, which increases difficulty in increasing the oscillating frequency of the ring oscillator.
"In the PLL circuit using the ring oscillator, when there is a slightest difference between the frequency of the external clock signal and the oscillating frequency of the ring oscillator, the difference is accumulated little by little and consequently a large phase difference maybe caused. To reduce such a phase difference, a correction operation for the oscillating frequency needs to be constantly performed, which increases the power consumption.
"With this background, a semiconductor device including a multiplier oscillator that can generate an internal clock signal with a high frequency without using a ring oscillator has been demanded."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In one embodiment, there is provided a semiconductor device that comprises: a plurality of delay circuits connected in series, the delay circuits including an input-stage delay circuit receiving an input clock signal and an output-stage delay circuit outputting an output clock signal, each of the delay circuits representing a delay amount responsive to an operating voltage supplied thereto; a regulator circuit controlling the operating voltage to be supplied to each of the delay circuits in response to a phase relationship between the input clock signal and the output clock signal; and a synthesizing circuit configured to synthesize clock signals supplied to selected ones of the delay circuits to generate an internal clock signal.
"In another embodiment, there is provided a method that comprises: electrically connecting N delay circuits in series, N being two or more integers; controlling a level of an operating voltage to be supplied to each of the delay circuits so that a delay amount of each of the delay circuits becomes 1/N of a cycle of an input clock signal supplied to a leading one of the delay circuits; and responding to signals to be respectively delayed by the delay circuits to generate an internal clock signal having a frequency that is N/2 times as large as the input clock signal.
"In still another embodiment, such a device is derived that comprises: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, the delay circuits being coupled in series such that the output node of a preceding one of the delay circuits is coupled to the input node of the succeeding one of the delay circuits, the input node of a leading one of the delay circuits receiving a first clock signal, the output node of a last one of the delay circuits producing a second clock signal, the first power node of each of the delay circuits being connected to a first power line, and the second power node of each of the delay circuits being connected to a second power line; and a control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention;
"FIG. 2 is a block diagram showing a configuration of the multiplier oscillator shown in FIG. 1;
"FIG. 3 is a circuit diagram of the variable delay circuit shown in FIG. 2;
"FIG. 4 is a circuit diagram of the delay circuits shown in FIG. 3;
"FIGS. 5A to 5D are explanatory diagrams of operations of the variable delay circuit shown in FIG. 2;
"FIG. 6 is a circuit diagram of the waveform synthesis circuit shown in FIG. 2;
"FIG. 7 is a waveform chart for explaining an operation of the waveform synthesis circuit;
"FIGS. 8A to 8D are waveform charts for explaining an influence in a case where the clock signal CLK0 and the clock signal CLK8 are out of phase;
"FIGS. 9A to 9F are a waveform charts for explaining a problem occurred in the case where the target edge is more than one clock cycle after source edge;
"FIG. 10 is a circuit diagram of the reference-edge detection circuit shown in FIG. 2;
"FIGS. 11A to 11C are waveform charts for explaining an operation of the reference-edge detection circuit;
"FIG. 12 is a block diagram showing a configuration of a DLL circuit using the multiplier oscillator;
"FIG. 13 is a circuit diagram of the delay line shown in FIG. 12;
"FIGS. 14A and 14B are waveform charts for explaining rise time and the fall time of the inverter circuit shown in FIG. 13;
"FIG. 15 is a waveform chart for explaining a problem in a case where a clock signal has high frequency; and
"FIG. 16 is a block diagram showing a configuration of another DLL circuit using the multiplier oscillator."
For additional information on this patent application, see:
Keywords for this news article include: Electronics, Semiconductor,
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