News Column

Researchers Submit Patent Application, "Power Switch Wafer Test Method", for Approval

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Sato, Shigeki (Matsumoto-city, Nagano, JP), filed on February 17, 2012, was made available online on February 13, 2014.

The patent's assignee is Fuji Electric Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a wafer test method of a power switch integrally formed on a semiconductor substrate.

"A power switch integrally formed on a semiconductor substrate is used in, for example, an automobile internal combustion engine ignition system. A configuration example of an internal combustion engine ignition system using a power switch is shown in FIG. 4.

"The internal combustion engine ignition system shown in FIG. 4 is configured of a power switch 11, an engine control unit (hereafter called an ECU (Electronic Control Unit)) 15, a battery power supply 16, an ignition coil 17, and a spark plug 18. By on (energizing) and off (cutting off) controlling a primary current flowing through a primary side coil of the ignition coil 17 connected to the battery power supply 16 using the power switch 11, a high voltage is induced in a secondary side coil, and a spark discharge is generated in the spark plug 18. Also, the turning on and off of the power switch 11 is controlled by an on-off signal from the ECU 15.

"The power switch 11 shown in FIG. 4 is configured of a power switch unit 10 and a control unit 14, and has a collector terminal (hereafter called a C-terminal) 4 connected to the primary side coil of the ignition coil 17, a gate terminal 8 connected to the ECU 15, and an emitter terminal 9 connected to a ground potential (hereafter called GND). The power switch unit 10 is configured of a main IGBT (Insulated Gate Bipolar Transistor) 1, a current detecting IGBT 2, and a gate resistor circuit 3, while the control unit 14 is configured of a current detector circuit 12 and gate drive circuit 13.

"Herein, the power switch 11 shown in FIG. 4 may be of a one-chip configuration wherein the power switch unit 10 and control unit 14 are integrally formed on the same semiconductor substrate, or may be of a two-chip configuration wherein the power switch unit 10 and control unit 14 are each formed on a separate semiconductor substrate.

"In the case of a two-chip configuration, connection places forming connection points of the power switch unit 10 and control unit 14, which are a gate terminal (hereafter called a G-terminal) 5, a main IGBT 1 emitter terminal (hereafter called an E1-terminal) 6, and a current detecting IGBT 2 emitter terminal (hereafter called an E2-terminal) 7, are each configured by connecting with connecting means such as wire bonding. Also, in the case of a one-chip configuration, the G-terminal 5, E1-terminal 6, and E2-terminal 7 forming the connection points of the power switch unit 10 and control unit 14 are each used as measurement test terminals at a time of a wafer test.

"Also, the power switch 11 shown in FIG. 4 is such that a current limiting function that limits the primary current is provided with an object of preventing burnout of the ignition coil 17 due to a primary current overcurrent, and of securing spark discharge stability when starting-up. The current limiting function is realized by means of detecting the primary current with the current detecting IGBT 2 and current detector circuit 12 and means of controlling the gate voltage of the main IGBT 1 and current detecting IGBT 2 with the gate drive circuit 13 and gate resistor circuit 3 in response to the primary current detection result.

"Herein, the primary current flowing through the primary side coil of the ignition coil 17 flows divided into a main current, which flows from the C-terminal 4 of the power switch unit 10 through the main IGBT 1 E1-terminal 6 and the emitter terminal 9, and a detected current, which flows from the C-terminal 4 of the power switch unit 10 through the current detecting IGBT 2 E2-terminal 7, the current detector circuit 12, and the emitter terminal 9. Further, the current ratio (main current flowing through main IGBT 1/detected current flowing through current detecting IGBT 2) thereof is normally set to be 100 or greater.

"In the internal combustion engine ignition system, the current ratio (main current/detected current) of the primary current flowing through the power switch unit 10 of the power switch 11 is an important characteristic for the primary current current control function, and is also measured in characteristic tests on the power switch 11. Technology whereby the reference voltage of a current control unit is regulated based on the results of measuring the main current and detected current in order to adjust the current ratio (main current/detected current), which is an important characteristic, to the design value is disclosed in PTL 1 (identified further on).

"Next, with regard to a wafer test method for the current ratio (main current/detected current) of the primary current in the power switch 11 shown in FIG. 4, a description will be given, using FIG. 5 and FIG. 6, of a heretofore known general test circuit and test method. Herein, as previously described, the power switch 11 has the power switch unit 10 and control unit 14, and is configured of one chip or two chips, but in the following description of the power switch 11 current ratio (main current/detected current) wafer test method, the power switch 11 is such that the control unit 14 is omitted (the function thereof is irrelevant when measuring the current ratio), and the description will be given with only the power switch unit 10 shown in detail.

"FIG. 5 is a wafer test circuit for measuring the main current flowing through the main IGBT 1 of the power switch unit 10 in the power switch 11, and is configured of the power switch unit 10, a tester 20, and a tester prober 21. The tester prober 21 has a tester prober stage 22, on which is set a test wafer of the power switch unit 10, and a probe card 23, which connects the measuring terminals of the tester 20 to the terminals of the test wafer of the power switch unit 10.

"Next, a description will be given of a method of measuring the main current of the main IGBT 1 using the wafer test circuit shown in FIG. 5. Firstly, an E-V_t terminal of the tester 20 is connected to an E-V_p terminal of the probe card 23, and connected to the E1-terminal (pad) 6 on the power switch unit 10 wafer via a probe connected to the E-V_p terminal of the probe card 23, whereby the E1-terminal 6 is set to a reference potential (normally GND).

"Next, a G-V_t terminal of the tester 20 is connected to a G-V_p terminal of the probe card 23, and connected to the G-terminal (pad) 5 on the power switch unit 10 wafer via a probe connected to the G-V_p terminal of the probe card 23, thereby applying a constant voltage Vo (V) at which the main IGBT 1 is turned on. Furthermore, a C-I_t terminal of the tester 20 is connected to the tester prober stage 22 (given C-I_s as a terminal name), and connected to the C-terminal 4 on the back surface of the power switch unit 10 wafer (a wafer back surface electrode corresponds to the C-terminal 4), thereby applying a constant current Io (A) to the main IGBT 1. Further, the current flowing through the E1-terminal 6 is connected via an E-1_p terminal of the probe card 23 to an E-1_t terminal of the tester 20, and a main current Im (A) flowing through the main IGBT 1 is measured.

"FIG. 6 is a wafer test circuit for measuring the detected current flowing through the current detecting IGBT 2 of the power switch unit 10 in the power switch 11 and, in the same way as in FIG. 5, is configured of the power switch unit 10, tester 20, and tester prober 21. The tester prober 21 has the tester prober stage 22, on which is set a test wafer of the power switch unit 10, and the probe card 23, which connects the measuring terminals of the tester 20 to the terminals of the test wafer of the power switch unit 10.

"Next, a description will be given of a method of measuring the detected current of the current detecting IGBT 2 using the wafer test circuit shown in FIG. 6. Firstly, the E-V_t terminal of the tester 20 is connected to the E-V_p terminal of the probe card 23, and connected to the E2-terminal (pad) 7 on the power switch unit 10 wafer via the probe connected to the E-V_p terminal of the probe card 23, whereby the E2-terminal 7 is set to a reference potential (normally GND). Next, the G-V_t terminal of the tester 20 is connected to the G-V_p terminal of the probe card 23, and connected to the G-terminal (pad) 5 on the power switch unit 10 wafer via the probe connected to the G-V_p terminal of the probe card 23, thereby applying the constant voltage Vo (V) at which the current detecting IGBT 2 is turned on. Furthermore, the C-I_t terminal of the tester 20 is connected via the tester prober stage 22 (given C-I_s as a terminal name) to the C-terminal 4 on the back surface of the power switch unit 10 wafer (the wafer back surface electrode corresponds to the C-terminal 4), thereby applying the constant current Io (A) to the current detecting IGBT 2. Further, the current flowing through the E2-terminal 7 is connected via the E-1_p terminal of the probe card 23 to the E-1_t terminal of the tester 20, and a detected current Is (A) flowing through the current detecting IGBT 2 is measured.

"Then, the current ratio (main current/detected current) of the power switch unit 10 in the power switch 11 is obtained by calculating main current Im (A)/detected current Is (A) from the main current Im (A) flowing through the main IGBT 1 measured using the wafer test circuit of FIG. 5 and the detected current Is (A) flowing through the current detecting IGBT 2 measured using the wafer test circuit of FIG. 6."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The invention, having been contrived bearing in mind the heretofore described problems, has an object of providing a power switch wafer test method whereby it is possible, in a power switch wherein a main IGBT and a current detecting IGBT, whose collector terminal and gate terminal are connected respectively to the collector terminal and gate terminal of the main IGBT and which detects the current value of the main IGBT, are integrally formed on the same semiconductor substrate, to test the current ratio (main current/detected current) between a main current flowing through the main IGBT and a detected current flowing through the current detecting IGBT, in the same way as in an actual operating condition, using a simple method.

"In order to solve the heretofore described problems, a power switch wafer test method of the invention is such that a resistor is connected between a main IGBT emitter terminal pin and a current detecting IGBT emitter terminal pin of a probe card used in a wafer test, a voltage difference is provided between a main IGBT emitter terminal and a current detecting IGBT emitter terminal, and a wafer test is carried out in a condition wherein the main IGBT and current detecting IGBT are turned on simultaneously, whereby a current ratio (main current/detected current) the same as in an actual operating condition is obtained.

"That is, the power switch wafer test method of the invention is a wafer test method of a power switch having a main IGBT and a current detecting IGBT, of which a collector terminal and gate terminal are connected respectively to a collector terminal and gate terminal of the main IGBT and which detects a current value of the main IGBT, wherein the main IGBT and current detecting IGBT are integrally formed on the same semiconductor substrate, and is characterized in that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and a current ratio (main current/detected current) between a main current of the main IGBT and a detected current of the current detecting IGBT is calculated from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current.

"Also, the power switch wafer test method of the invention is a wafer test method of a power switch having a main IGBT and a current detecting IGBT, of which a collector terminal and gate terminal are connected respectively to a collector terminal and gate terminal of the main IGBT and which detects a current value of the main IGBT, wherein the main IGBT and current detecting IGBT are integrally formed on the same semiconductor substrate, and is characterized in that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, a total current of a main current of the main IGBT flowing from the emitter terminal of the main IGBT and a detected current of the current detecting IGBT is detected, the detected current of the current detecting IGBT is detected from the voltage across the resistance means, and a current ratio (main current/detected current) between the main current of the main IGBT and the detected current of the current detecting IGBT is calculated.

"Also, the resistance means of the power switch wafer test method of the invention is characterized by being connected between terminals of a wafer test probe card corresponding to the emitter terminal of the main IGBT and the emitter terminal of the current detecting IGBT.

"Advantageous Effects of Invention

"The power switch wafer test method of the invention is such that, by a resistor being connected between a main IGBT emitter terminal pin and a current detecting IGBT emitter terminal pin of a wafer measuring probe card, a voltage difference being provided between a main IGBT emitter terminal and a current detecting IGBT emitter terminal, and a wafer test being carried out in a condition wherein the main IGBT and current detecting IGBT are turned on simultaneously, it is possible to easily measure a current ratio (main current/detected current) in a condition the same as an actual operation.

"The heretofore described and other objects, characteristics, and advantages of the invention will be made clear by the following description relating to the attached drawings representing an embodiment preferred as an example of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a diagram showing a configuration example of a wafer test circuit used for a power switch current ratio wafer test method according to the invention.

"FIG. 2 is a test flow diagram showing the procedure of a first wafer test method relating to the power switch wafer test method according to the invention.

"FIG. 3 is a test flow diagram showing the procedure of a second wafer test method relating to the power switch wafer test method according to the invention.

"FIG. 4 is a diagram showing a configuration example of an internal combustion engine ignition system using a power switch.

"FIG. 5 is a diagram showing a wafer test circuit for measuring a main current in the case of a heretofore known power switch wafer test method.

"FIG. 6 is a diagram showing a wafer test circuit for measuring a detected current in the case of the heretofore known power switch wafer test method."

For additional information on this patent application, see: Sato, Shigeki. Power Switch Wafer Test Method. Filed February 17, 2012 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5480&p=110&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Electronics, Semiconductor, Fuji Electric Co. Ltd..

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Source: Electronics Newsweekly


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