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Researchers Submit Patent Application, "Method of Producing Semiconductor Device, Solid-State Imaging Device, Method of Producing Electric Apparatus,...

February 26, 2014



Researchers Submit Patent Application, "Method of Producing Semiconductor Device, Solid-State Imaging Device, Method of Producing Electric Apparatus, and Electric Apparatus", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Miyoshi, Yasufumi (Kanagawa, JP), filed on October 11, 2013, was made available online on February 13, 2014.

The patent's assignee is Sony Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a method of producing a semiconductor device, a solid-state imaging device, a method of producing an electric apparatus, and an electric apparatus.

"Isolation using an impurity diffusion layer is a technology of isolating a unit pixel in a solid-state imaging device such as a CCD imaging device. When an n-type photosensor including a photodiode forms a unit pixel, a lattice-shaped p-type impurity diffusion layer is formed as an element isolation region isolating unit pixels from one other. Such an element isolation region is formed by ion implantation between unit pixels through an ion implantation mask.

"A unit pixel has been reduced in size in recent years. Accordingly, in order to increase a photosensor area for increasing an amount of light incident on each photosensor and increasing sensitivity of an imaging device, a deep and narrow element isolation region is demanded.

"A certain amount of ion implantation energy may be necessary to ion implant an impurity between unit pixels and form a deep element isolation region. This increases an aspect ratio which may be necessary to form an opening in an ion implantation mask (hereinafter II mask). Currently, an II mask structure having a desired high aspect ratio may not be obtained using a photoresist as a mask material. Therefore, RIE (reactive ion etching) is typically used to form an II hard mask of SiO.sub.2 having a desired structure.

"FIGS. 1A to 1C are schematic process views of a method of producing a solid-state imaging device using an II hard mask in the related art. This example illustrates a schematic process of forming an element isolation region in a solid-state imaging device, where the element isolation region is formed by ion implantation.

"First, as shown in FIG. 1A, an SiN film (hereinafter P-SiN film) 21 by plasma CVD (chemical vapor deposition), an SiO.sub.2 film 22 and a resist mask 23 are formed on a surface of an Si substrate 20 with an n-type photosensor formed thereon, for example. Here, the photosensor formed on the Si substrate 20 is not shown. The P-SiN film 21 formed on the Si substrate 20 is used as a stopper layer, and the SiO.sub.2 film 22 is used as an II hard mask. The SiO.sub.2 film 22 forms an II hard mask having a high aspect ratio and thus has a thickness of 5 .mu.m, for example. The resist mask 23 is formed as a pattern having a slit-like opening 25 formed by pattern exposure and development. Here, the opening 25 is formed to have a width of 0.5 .mu.m, for example.

"Next, as shown in FIG. 1B, the SiO.sub.2 film 22 is etched through the opening 25 of the resist mask 23 to form an II hard mask 26 having a high aspect ratio.

"Next, as shown in FIG. 1C, a p-type impurity, for example, is ion implanted into the Si substrate 20 through the II hard mask 26 having a high aspect ratio and thermally diffused to form an element isolation region 24. Since an impurity is ion implanted into the Si substrate 20 through the II hard mask 26 having a high aspect ratio, a narrow and deep p-type diffusion region may be formed as the element isolation region 24.

"In addition to a demand for a pixel reduced in size, an element isolation region is also demanded to be narrow, and therefore an II hard mask opening is demanded to be as narrow as 0.3 .mu.m or less. FIGS. 2A to 2C show a schematic configuration of a solid-state imaging device having an II hard mask having an aspect ratio of 20, for example. In FIGS. 2A to 2C, parts corresponding to those of FIG. 1 are indicated by the same symbols and repeated description thereof is omitted. In the case of forming the II hard mask 26 as shown in FIGS. 1A to 1C, it is difficult to vertically process the SiO.sub.2 film by RIE when the aspect ratio reaches about 20. In this case, the II hard mask 26 may not have an ideal vertical shape as shown in FIG. 2A but has a tapered shape as shown in FIG. 2B or a bowing shape as shown in FIG. 2C. When the opening of the II hard mask 26 has a tapered or bowing shape, ion implantation is performed in accordance with a widest width of the opening shape. Therefore, distribution of an impurity diffusion layer is wider than a desired distribution indicated by a broken line as shown in FIG. 2B or 2C. Accordingly, in the solid-state imaging device, the element isolation region 24 becomes wider than the desired distribution region indicated by the broken line and narrows an adjacent photosensor region (not shown), so that sensitivity of the imaging device to incident light is decreased, disadvantageously.

"Japanese Unexamined Patent Application Publication No. 9-162137 discloses an ion implantation method including reducing a size of an opening on a lower edge of the opening of a mask pattern by reflowing to control a minute area of an ion implantation region and then implanting ions in a desired position."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "However, a mask pattern formed of a resist layer described in Japanese Unexamined Patent Application Publication No. 9-162137 has an opening width of 1 .mu.m and a thickness of 1 to 2 .mu.m and has a low aspect ratio. Accordingly, deep ion implantation may not be expected.

"As described above, when a hard mask having a large thickness is used to perform deep ion implantation, it is difficult to accurately form a mask pattern having a smaller opening width, and therefore desirable ion implantation into a narrow region may not be achieved, disadvantageously.

"In view of the aforementioned points, it is desirable to provide a method of producing a semiconductor device including a narrow and deep impurity region and a solid-state imaging device including the same. Further, it is desirable to provide a method of producing an electric apparatus including a narrow and deep impurity region and an electric apparatus including the same.

"According to an embodiment of the present invention, there are provided a method of producing a semiconductor device and a method of producing an electric apparatus. Each of the methods includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.

"In a method of producing a semiconductor device and a method of producing an electric apparatus according to an embodiment of the present invention, a sacrificial film is formed above a side surface of an opening of a first hard mask, a second hard mask is formed and then the sacrificial film is removed, so that the second hard mask may be formed by self-alignment.

"According to an embodiment of the present invention, there are provided a solid-state imaging device and an electric apparatus, each including a unit pixel having a second conductivity-type photosensor and a first conductivity-type element isolation region having both edges covered by a second conductivity-type impurity and isolating the unit pixel.

"In a solid-state imaging device and an electric apparatus according to an embodiment of the present invention, both edges of a first conductivity-type element isolation region are covered by a second conductivity-type impurity, so that the element isolation region may not become widened and accordingly a photosensor is not narrowed.

"In a method of producing a semiconductor device and a method of producing an electric apparatus according to an embodiment of the present invention, first and second hard masks are used, so that an impurity region is narrowed and a deep impurity region is formed, in the case of using a mask having a high aspect ratio.

"In a solid-state imaging device and an electric apparatus according to an embodiment of the present invention, both edges of a first conductivity-type element isolation region are covered by a second conductivity-type impurity, so that the element isolation region is finally formed as a deep and narrow region and it is possible to suppress a decrease in sensitivity due to reduction of a photosensor in size.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1A to 1C are schematic process views of a method of forming an element isolation region in a solid-state imaging device of the related art.

"FIG. 2A shows an example of an ideal shape of an element isolation region when using an II hard mask having an opening with a high aspect ratio in a solid-state imaging device, and FIGS. 2B and 2C show an example of a defective shape of the element isolation region.

"FIGS. 3A to 3D are schematic process views (1) showing a method of producing a semiconductor device according to a first embodiment of the present invention.

"FIGS. 4E to 4G are schematic process views (2) showing a method of producing a semiconductor device according to a first embodiment of the present invention.

"FIGS. 5A to 5C are schematic process views (1) showing a method of producing a semiconductor device according to a second embodiment of the present invention.

"FIGS. 6D to 6F are schematic process views (2) showing a method of producing a semiconductor device according to a second embodiment of the present invention.

"FIGS. 7G to 7I are schematic process views (3) showing a method of producing a semiconductor device according to a second embodiment of the present invention.

"FIG. 8 is a schematic cross-sectional view of a solid-state imaging device according to a third embodiment of the present invention.

"FIG. 9 is a schematic cross-sectional view of a camera according to an embodiment of the present invention."

For additional information on this patent application, see: Miyoshi, Yasufumi. Method of Producing Semiconductor Device, Solid-State Imaging Device, Method of Producing Electric Apparatus, and Electric Apparatus. Filed October 11, 2013 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2750&p=55&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Electronics, Semiconductor, Sony Corporation.

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Source: Electronics Newsweekly


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