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Researchers Submit Patent Application, "Interconnect Formation Using a Sidewall Mask Layer", for Approval

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Hu, Xiang (Clifton Park, NY); Wang, Mingmei (Ballston Lake, NY); Huang, Liu (Malta, NY), filed on July 31, 2012, was made available online on February 13, 2014.

The patent's assignee is Globalfoundries Inc.

News editors obtained the following quote from the background information supplied by the inventors: "This invention relates generally to the field of semiconductors, and more particularly, to manufacturing approaches used in forming openings during interconnect processing of integrated circuits and other devices.

"The semiconductor manufacturing process typically includes two major components, namely the Front-End-of-Line (FEOL), which includes the multilayer process of forming semiconductor devices (transistors, etc.) on a semiconductor substrate, and the Back-End-Of-Line (BEOL), which includes the metallization after the semiconductor devices have been formed. Like all electronic devices, semiconductor devices in a microchip, such as an integrated circuit (IC), need to be electronically connected through wiring. In an integrated circuit, such wiring is done through multilayer metallization on top of the multilayered semiconductor devices formed on the semiconductor substrate. The complexity of this wiring becomes appreciable as there may be hundreds of millions or more semiconductor devices (e.g., transistors in particular) formed on a single IC. Proper connection of these devices is accomplished by multilayer metallization. Each metallization layer consists of a grid of metal lines sandwiched between one or more dielectric layers for electrical integrity. Modern semiconductor manufacturing processes can involve multiple metallization layers.

"As scaling of microelectronic devices approaches sub 30 nm nodes, many material and module process challenges in BEOL plasma patterning have been reported. One of the methods that has gained traction over recent years for enabling sub 20 nm feature patterning is the Trench First Metal Hard Mask (TFMHM) scheme. While this scheme solves or mitigates many challenges that are inherent with the Via First Trench Last (VFTL) Scheme, it introduced other dielectric reactive ion etching (RIE) process and hardware challenges. One of the root causes of the former is the fact that all patterns and materials are exposed to plasma at the same time. As such, the simultaneous control of via, trench and chamfer profiles (i.e. Critical Dimensions, depth, taper profile, etc), the need to control selectivity between multiple patterning layer (Titanium Nitride (TiN), tetra-ethyl-ortho-silane (TEOS), ultra low k (ULK), Barrier cap, etc), and ULK damage control has become more pertinent in the dielectric etch. As a direct result of such tight process guidelines, the hardware challenges arise and new dimensions in process controls are needed. The prolonged exposure of the TiN to the plasma created the need for more robust production worthy hardware. The required selectivity of the materials necessitate temperature controllable chucks. The more complex patterning techniques require ULK preservation and other uniformity controls."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In general, embodiments of the invention provide an approach for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask layer following removal of a previously formed planarization layer. The sidewall mask layer is conformally deposited on the hard mask in a merged via region of the semiconductor device, and acts like a sacrificial layer to protect the hard mask layer during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch. The sidewall mask layer improves the hard mask margin for the via etch without sacrificing metal filling capability and defect-related performance.

"One aspect of the present invention includes a method for forming a device, the method including: providing an integrated circuit (IC) structure including: an interdielectric layer (IDL) formed over a substrate and a capping layer; a hard mask layer formed over the IDL; a hard mask formed over the hard mask layer, the hard mask including a plurality of openings formed therein; and a planarization layer formed over the hard mask in a merged via region of the device; removing the planarization layer exposed by an opening in a masking structure formed over the planarization layer; and forming a sidewall mask layer over the hard mask.

"Another aspect of the present invention includes a method for interconnect formation, the method including: providing a hard mask formed over an interdielectric layer (IDL) of an integrated circuit (IC) structure, the hard mask including a plurality of openings formed therein; removing a planarization layer formed over the hard mask; forming a sidewall mask layer over the hard mask in a merged via region of the IC structure; and forming a plurality of vias in the IC structure through the plurality of openings of the hard mask.

"Another aspect of the present invention provides a method for forming a semiconductor device, the method including: removing an organic planarization layer formed over a hard mask of the semiconductor device; forming a sidewall mask layer over the hard mask in a merged via region of the device; etching the sidewall mask layer to expose an interdielectric layer of the device; and forming a plurality of vias in the semiconductor device through a plurality of openings of the hard mask.

BRIEF DESCRIPTION OF THE DRAWINGS

"These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:

"FIG. 1A shows a cross-sectional view of a prior art semiconductor device following a via etch;

"FIG. 1B shows a top view of the prior art semiconductor device of FIG. 1A following the via etch;

"FIG. 2A shows a cross-sectional view of a prior art semiconductor device following a trench etch;

"FIG. 2B shows a top view of the prior art semiconductor device of FIG. 2A following the trench etch;

"FIG. 3 shows a cross-sectional view of a device during its manufacture according to illustrative embodiments;

"FIG. 4 shows a cross-sectional view of the device following a planarization removal process according to illustrative embodiments;

"FIG. 5 shows a cross-sectional view of the device following formation of a sidewall mask layer according to illustrative embodiments;

"FIG. 6 shows a cross-sectional view of the device following removal of a portion of the sidewall mask layer according to illustrative embodiments;

"FIG. 7 shows a cross-sectional view of the device following a via etch according to illustrative embodiments;

"FIG. 8A shows a cross-sectional view of the device following removal of any remaining portions of the sidewall mask layer according to illustrative embodiments;

"FIG. 8B shows a top view of the device of FIG. 8A following removal of any remaining portions of the sidewall mask layer according to illustrative embodiments;

"FIG. 9A shows a cross-sectional view of the device following a trench etch according to illustrative embodiments; and

"FIG. 9B shows a top view of the device of FIG. 9A following the trench etch according to illustrative embodiments.

"The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements."

For additional information on this patent application, see: Hu, Xiang; Wang, Mingmei; Huang, Liu. Interconnect Formation Using a Sidewall Mask Layer. Filed July 31, 2012 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2679&p=54&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Electronics, Semiconductor, Globalfoundries Inc..

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Source: Electronics Newsweekly


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