News Column

Researchers Submit Patent Application, "Inspecting a Wafer And/Or Predicting One Or More Characteristics of a Device Being Formed on a Wafer", for...

February 26, 2014



Researchers Submit Patent Application, "Inspecting a Wafer And/Or Predicting One Or More Characteristics of a Device Being Formed on a Wafer", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Marcuccilli, Gino (Glasgow, GB); Widmann, Amir (Sunnyvale, CA); Chang, Ellis (Saratoga, CA); Robinson, John (Austin, TX); Park, Allen (San Jose, CA), filed on March 2, 2013, was made available online on February 13, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "This invention generally relates to methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer.

"The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.

"Fabricating semiconductor devices such as integrated circuits involves forming multiple layers on a wafer. Different structures are formed on different layers of the wafer, and some structures on different layers are intended to be electrically connected to each other while other structures on different layers are intended to be insulated from one another. If the structures on one layer are not properly aligned with other structures of other layers, the misalignment of the structures can prevent the proper electrical connection of some structures and/or the proper insulation for other structures. Therefore, measuring and controlling the alignment of multiple layers on a wafer is important in the successful manufacture of working semiconductor devices.

"Generally, the alignment of one layer to another layer on a wafer is determined by the alignment of the wafer in an exposure step of a lithography process performed on the wafer. In particular, since the lithography process involves forming patterned features in a resist material that are then transferred to a device material using other fabrication processes, the lithography process generally controls where the patterned features (and therefore where device structures formed from the patterned features) are formed on the wafer. Therefore, measuring and controlling alignment of the wafer and thereby overlay of features on one layer with respect to features on another layer before, during, and/or after the lithography process is a critical step in the fabrication process.

"Parameters of the lithography process other than overlay also affect the resulting patterned features formed on the wafer. For example, the focus and dose of the exposure tool used in the lithography process can affect various characteristics of the patterned features such as critical dimension, side wall angle, and height. If the patterned features are not formed within specifications for such characteristics, device structures formed from the patterned features may not be properly insulated from one another or properly connected with one another. In addition, such characteristics can also affect electrical characteristics of devices formed on the wafer. Therefore, it is important to monitor and control multiple parameters of the lithography process to ensure that working devices are fabricated and also to ensure that devices having suitable functionality are fabricated.

"Accordingly, it would be advantageous to develop systems and/or methods that can be used to improve the devices fabricated on wafers by eliminating design problems before the devices are fabricated and monitoring and controlling the lithography process."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The following description of various embodiments is not to be construed in any way as limiting the subject matter of the appended claims.

"One embodiment relates to a method for inspecting a wafer. The method includes acquiring images for multiple die printed on a wafer. Each of the multiple die is printed by performing a double patterning lithography process on the wafer. The multiple die include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay. The method also includes comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values. In addition, the method includes detecting defects in the multiple die printed at the modulated values based on results of the comparing step.

"Another embodiment relates to a method for predicting one or more characteristics of a device being formed on a wafer. The method includes performing metrology on one or more die formed on a wafer using a lithography process. The method also includes determining overlay errors, focus errors, dose errors, or some combination thereof of the lithography process in the one or more die based on results of the metrology. In addition, the method includes simulating one or more characteristics, such as contour, of a device being formed from the one or more die by applying the overlay errors, focus errors, dose errors, or some combination thereof to design data for the one or more die.

"Each of the steps of the method embodiments described above may be performed as described further herein. The methods described above may include any other step(s) of any other method(s) described herein and may be performed using any of the systems described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

"Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

"FIG. 1 is a schematic diagram illustrating one embodiment of multiple die printed on a wafer, which include two or more die printed at nominal values of a parameter of a double patterning lithography process and one or more die printed at modulated values of the parameter;

"FIG. 2 is a schematic diagram illustrating a side view of one embodiment of a system configured for inspecting a wafer;

"FIG. 3 is a block diagram illustrating one embodiment of a non-transitory computer-readable medium storing program instructions executable on a computer system for performing one or more methods described herein; and

"FIG. 4 is a schematic diagram illustrating a side view of one embodiment of a system configured for predicting one or more characteristics of a device being formed on a wafer.

"While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims,"

For additional information on this patent application, see: Marcuccilli, Gino; Widmann, Amir; Chang, Ellis; Robinson, John; Park, Allen. Inspecting a Wafer And/Or Predicting One Or More Characteristics of a Device Being Formed on a Wafer. Filed March 2, 2013 and posted February 13, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3904&p=79&f=G&l=50&d=PG01&S1=20140206.PD.&OS=PD/20140206&RS=PD/20140206

Keywords for this news article include: Patents, Electronics, Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools