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Patent Issued for Structure and Method of Fabricating a Transistor Having a Trench Gate

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Smith, Michael (Boise, ID); Helm, Mark (Boise, ID); Prall, Kirk (Boise, ID), filed on January 31, 2011, was published online on February 11, 2014.

The patent's assignee for patent number 8647949 is Round Rock Research, LLC (Jersey City, NJ).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to integrated circuit transistors. In particular, the invention relates to a structure and method of fabricating a transistor having a trench gate.

"Integrated circuit designers often desire to increase the density of elements within an integrated circuit by reducing the size of the individual elements and reducing the separation distance between neighboring elements. One example of a common integrated circuit element is a transistor, which can be found in many devices, such as memory circuits, processors, and the like. A typical integrated circuit transistor comprises a source, a drain, and a gate formed at the surface of the substrate.

"Although it is generally desirable to reduce the size of integrated circuit transistors, the ability to shrink certain dimensions, such as the length of the gate, can be limited due to the voltage levels needed to perform certain operations. In one example, a relatively high amount of voltage can be required by some transistors used in flash memory to perform certain operations, such as program, read, and erase. One approach for reducing the size of such transistors while maintaining the gate length necessary to satisfy the voltage requirements is to form the transistor gate as a trench below the surface of the substrate.

"In one example, a transistor gate can be implemented as a U-shaped trench connecting the source and the drain. Such a U-shaped gate trench maintains the gate length while allowing the gate surface area to decrease."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Present fabrication methods for a transistor with a U-shaped gate trench produce a transistor structure that is prone to parasitic current traveling from the source to the drain along the gate trench sidewall due to unetched substrate material present at the gate trench sidewall. In addition, it is difficult to maintain isolation between gate trench bottoms of neighboring transistors using current fabrication techniques. A unique transistor structure and a fabrication process are disclosed to prevent unetched substrate material from forming along the gate trench sidewall and to facilitate isolation of neighboring transistors.

"In one embodiment of the present invention, a semiconductor device comprises a transistor having a source and a drain comprising a substrate material and a gate trench between the source and the drain. The device also comprises an isolation trench filled with a nonconductive material surrounding the transistor. The gate trench has sidewalls comprising the nonconductive material, which are substantially free of the substrate material.

"In another embodiment, an integrated circuit transistor comprises a source, a drain, and a gate trench between the source and the drain. The gate trench has nonconductive sidewalls and has a first depth. The transistor is surrounded by an isolation trench having a second depth that is greater than the first depth. The nonconductive sidewalls of the gate trench are formed at a point toward the middle of the gate trench and away from the isolation trench.

"In another embodiment, a method of forming a semiconductor element comprises providing a semiconductor substrate having a hard mask layer deposited thereon, patterning the hard mask layer with a first photo mask, and etching the semiconductor substrate to form an isolation trench having a first depth. The method further comprises patterning the hard mask layer with a second photo mask, and etching the semiconductor substrate to form a gate trench having a second depth and simultaneously etching the isolation trench to a third depth, wherein the third depth is greater than the second depth.

"In another embodiment, a method of fabricating a transistor comprises patterning a substrate with a first mask, forming an isolation trench in the substrate, and depositing a nonconductive material in the isolation trench. The method further comprises patterning the substrate with a second mask and forming a gate trench surrounded by a ridge of substrate material, wherein the ridge of substrate material is separated from a source, a drain, and a gate by a separation trench. The method further comprises filling the gate trench and the separation trench with the nonconductive material, patterning the nonconductive material with a third mask, and removing the nonconductive material from a region of the gate trench, thereby forming a trench with sidewalls comprising the nonconductive material."

For additional information on this patent, see: Smith, Michael; Helm, Mark; Prall, Kirk. Structure and Method of Fabricating a Transistor Having a Trench Gate. U.S. Patent Number 8647949, filed January 31, 2011, and published online on February 11, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=63&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3137&f=G&l=50&co1=AND&d=PTXT&s1=20140211.PD.&OS=ISD/20140211&RS=ISD/20140211

Keywords for this news article include: Electronics, Semiconductor, Round Rock Research LLC.

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Source: Electronics Newsweekly


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