The patent's inventors are Song, Eun-seok (Gwanak-gu, KR); Kim, Dong-han (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor package and a method of testing the semiconductor package. More particularly, the invention relates to a semiconductor package having a plurality of test pads disposed on the top and bottom surfaces of a substrate and a related method of testing the semiconductor package.
"The recent evolution of integrated semiconductor packages is one characterized by increasing size. Contemporary packages include structures that allow multiple semiconductor chips or multiple semiconductor (sub-)packages to be mounted within a single package. So-called system in package (SIP) or package on package (POP) devices are examples of this evolution.
"The incorporation of multiple semiconductor dies or multiple semiconductor packages within a single package has, up until now, necessarily resulted in an increase in the overall size of the semiconductor package. However, this outcome runs counter to the commercial trend of supplying increasingly sophisticated consumer electronics with increasingly small sizes. In order to satisfy the demand for smaller overall products, the size of constituent semiconductor package(s) must decrease.
"A principal driver in the conventional expansion of semiconductor packages is an increasing need for connection pads (or terminals). Terminals are often implemented by the provision of numerous solder balls in the semiconductor package such as the SIP or POP. Unfortunately, the resulting layout of solder balls and related collection of connection paths occupy a relatively large amount of space on a substrate implementing the package. As a result, numerous design efforts and fabrication experiments have been directed to the development of efficient layouts for connection terminals. Such efforts seek to facilitate the ongoing trend of overall product miniaturization.
"FIG. 1 is a bottom view of a typical semiconductor package including a layout of solder balls facilitating connection of various signals. In the illustrated example, a 9.times.9 array of solder balls is disposed on the bottom surface of a substrate 10 supporting a semiconductor package 1. Among the array solder balls, a first class of solder balls 12 are intended for user defined purposes (e.g., signal connection). A second class of solder balls 14 are provided to allow testing of the semiconductor package during manufacture. Such 'test only' solder balls 14, which are only used during manufacture of the semiconductor package, are thereafter labeled, `No connection or NC'. Nearly all contemporary semiconductor packages include test only-related solder balls.
"In addition to testing connections made through test only solder balls, semiconductor packages are also connected to a tester through a needle-like probe or so-called POGO pin. Certain basic functions of the circuits contained within the semiconductor package may be readily tested via these types of external probe testing methods. Whether a testing connection is made through a test only solder ball or an external probe, conventional semiconductor packages routinely provide such connections on only a single surface of the package, e.g., a bottom surface of a substrate supporting the package.
"Unfortunately, this conventional approach to test connection provision is becoming increasingly inadequate as the corresponding number of solder balls and connection pads continues to increase. Indeed efforts to decrease the size of the substrate and the overall semiconductor package are being defeated by the need for more test connections. This problem is becoming particularly acute in relation to the development of SIPs and POPs, including two or more semiconductor chips."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Embodiments of the invention provide a semiconductor package having test pads on both top and bottom surfaces of a substrate supporting a semiconductor package.
"In one embodiment, the invention provides a semiconductor package, comprising; a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads disposed on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surfaces of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.
"In another embodiment, the invention provides a method of testing a semiconductor package, wherein the semiconductor package comprises a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surfaces of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto. The method comprises; loading the semiconductor package into a tester, and performing electrical/functional testing of the semiconductor package using a test connector simultaneously connected to the plurality of test pads."
For the URL and additional information on this patent, see: Song, Eun-seok; Kim, Dong-han; Lee, Hee-seok. Semiconductor Package Having Test Pads on Top and Bottom Substrate Surfaces and Method of Testing Same. U.S. Patent Number 8647976, filed
Keywords for this news article include: Semiconductor,
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