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Patent Issued for Nonvolatile Semiconductor Memory Device Including a Via-Hole with a Narrowing Cross-Section and Method of Manufacturing the Same

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Kabushiki Kaisha Toshiba (Tokyo, JP) has been issued patent number 8648471, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Tabata, Hideyuki (Kawasaki, JP); Ito, Eiji (Yokohama, JP); Inoue, Hirofumi (Kamakura, JP).

This patent was filed on April 24, 2012 and was published online on February 11, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a multilayer-structured nonvolatile semiconductor device with stacked memory cells of the cross point type and method of manufacturing the same.

"Electrically erasable programmable nonvolatile memories include a flash memory as well known in the art, which comprises a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.

"On the other hand, technologies of pattering memory cells much finer include a resistance variable memory, which uses a variable resistor in a memory cell as proposed. Known examples of the variable resistor include a phase change memory element that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM element that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory element including resistors formed of a conductive polymer; and a ReRAM element that causes a variation in resistance on electrical pulse application (Patent Document 1: JP 2006-344349A, paragraph 0021).

"The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easier and three-dimensionally structured to achieve much higher integration advantageously (Patent Document 2: JP 2005-522045A).

"The above-described multilayer-structured memory of prior art requires formation of via-holes extending vertically to connect word and bit lines in each layer to a semiconductor substrate, layer by layer, which requires process steps of forming via-holes and increases the cost."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In an aspect the present invention provides a nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate, wherein the via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal beginning positions and terminating positions are connected to the first or second lines in different cell array layers.

"In another aspect the present invention provides a nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate, wherein the via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions include some via-holes connected to the first or second line in a certain cell array layer and other via-holes connected to the first or second line in a cell array layer different from the certain cell array layer.

"In another aspect the present invention provides a method of manufacturing nonvolatile semiconductor memory devices, comprising: forming plural cell array layers in multiple layers on a semiconductor substrate to form a cell array block, each cell array layer including a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; forming penetrated holes simultaneously, together with formation of the cell array block, after formation of plural cell array layers, the penetrated holes penetrating the plural cell array layers and penetrating the first or second lines in different cell array layers; and filling the simultaneously formed penetrated holes with a conductive material, thereby forming a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate."

For the URL and additional information on this patent, see: Tabata, Hideyuki; Ito, Eiji; Inoue, Hirofumi. Nonvolatile Semiconductor Memory Device Including a Via-Hole with a Narrowing Cross-Section and Method of Manufacturing the Same. U.S. Patent Number 8648471, filed April 24, 2012, and published online on February 11, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=53&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2619&f=G&l=50&co1=AND&d=PTXT&s1=20140211.PD.&OS=ISD/20140211&RS=ISD/20140211

Keywords for this news article include: Electronics, Semiconductor, Kabushiki Kaisha Toshiba.

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Source: Electronics Newsweekly


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