News Column

Patent Issued for Method of Forming Wiring and Method of Manufacturing Semiconductor Substrates

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Ohhira, Shinya (Osaka, JP), filed on February 17, 2011, was published online on February 11, 2014.

The patent's assignee for patent number 8647980 is Sharp Kabushiki Kaisha (Osaka, JP).

News editors obtained the following quote from the background information supplied by the inventors: "When wiring in semiconductor devices is reduced to a microscopic size so as to highly integrate the semiconductor devices, and when current density of the wiring is increased so as to improve operation speed of the semiconductor devices, a problem of the wiring becoming less reliable due to electromigration occurs.

"Al wiring, which is widely used in the current semiconductor devices, has a low electromigration resistance. Therefore, various materials for wiring to replace the Al wiring have been examined. Cu is attracting attention as one of the materials for wiring to replace Al.

"Methods of forming Cu wiring includes a method of forming a photoresist as a resist on a Cu thin film that is formed on a substrate, patterning the resist by the photolithography, and etching the thin film by isotropic wet etching.

"This method, however, causes a problem of reducing the width or height in part of the wiring as shown in FIG. 2(a), resulting in a disconnection of the wiring or an increase of resistance.

"This problem arises because a surface of the Cu thin film tends to have a surface reaction such as oxidation at a relatively low temperature, which makes the surface condition thereof not stable. Depending on the surface condition of the Cu thin film, adhesion between the Cu thin film and the photoresist may be significantly decreased.

"If the adhesion between the photoresist and the surface of the Cu thin film is weak, when forming the photoresist on the Cu thin film and patterning the photoresist, part of the resist comes off. Consequently, the above problem arises.

"As described above, if the resist is not adhered firmly to the surface of the Cu thin film, the wiring cannot be formed to the design dimensions (the width and the height of the wiring).

"Patent Document 1 discloses a technique of etching Cu in a shape of wiring by the RIE (Reactive Ion Etching) method, which is anisotropic etching.

"In this technique of forming the Cu wiring, as shown in FIG. 9(a), a TiN barrier layer 112 (lower barrier layer), a Cu layer 114, and a TiN barrier layer 116 (upper barrier layer) are deposited in this order on a base 110. Thereafter, an SiO.sub.2 etching mask 118a is formed on the TiN barrier layer 116, which is the upper barrier layer.

"Next, by the RIE method, the upper TiN barrier layer 116, the Cu layer 114, and the lower TiN barrier layer 112 are etched in this order in the shape of the wiring over the etching mask.

"Here, a mixed gas containing SiCl.sub.4, Cl.sub.2, and N.sub.2, for example, is used as an etching gas. As the upper TiN barrier layer 116, the Cu layer 114, and the lower TiN barrier layer 112 are etched as shown in FIG. 9(b) by controlling the atomic ratio of Si to Cl in the etching gas, an SiO.sub.xN.sub.y barrier layer as a sidewall barrier layer 122 is deposited on sidewalls of the etched layers.

"As described above, in the technique of forming the Cu wiring disclosed in Patent Document 1, when the Cu layer is etched, reaction products are formed from the etching mask and the reactive etching gas. The reaction products are deposited on side surfaces 1141 where the Cu layer is etched, forming the sidewall barrier layer 122.

"Therefore, the sidewall barrier layer 122 can be formed while etching the layers, thereby eliminating a heat treatment for forming the sidewall barrier layer 122. Consequently, the sidewall barrier layer 122 can be formed at such a low temperature that semiconductor elements are not degraded."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Problems to be Solved by the Invention

"If anisotropic dry etching is performed by the RIE method as in the technique described in Patent Document 1, finer patterning is possible as compared to the method in which the wiring is patterned by wet etching.

"The RIE method, however, requires a special device such as a vacuum chamber (reaction chamber 123 shown in FIGS. 9(a) and 9(b)), causing a problem of higher manufacturing cost.

"In addition, Cu has a low reaction vapor pressure and the reaction speed thereof is therefore very slow, causing the etching speed to be very slow in dry etching by the RIE method, which results in another problem of low productivity.

"The present invention was made in view of the above-mentioned problems, and aims at providing a method of forming the Cu wiring to design dimensions by employing wet etching.

"Means for Solving the Problems

"In order to solve the above-mentioned problems, a method of forming wiring includes: depositing a metal thin film that contains Cu on a base member; forming, on the metal thin film, an insulating film or a metal film that does not contain Cu (i.e., a film chosen from a group of (1) an insulating film and (2) a metal film that does not contain Cu); patterning a photoresist by photolithography on the insulating film or the metal film that does not contain Cu; etching the insulating film or the metal film that does not contain Cu by isotropic dry etching using the photoresist as an etching mask; and forming metal wiring by removing the photoresist after the insulating film or the metal film that does not contain Cu is etched, and etching the metal thin film by isotropic wet etching using the insulating film or the metal film that does not contain Cu as an etching mask so as to partially remove the metal thin film.

"In the method described above, the insulating film or the metal film that does not contain Cu is formed, as a liner film that has an etching selectivity, between the metal thin film that contains Cu and the photoresist.

"The surface condition of the insulating film or the metal film that does not contain Cu is less likely to cause a reaction such as oxidation as compared to that of Cu, and therefore is stable. Thus, the adhesion between the insulating film (or the metal film that does not contain Cu) and the photoresist is stronger than the adhesion between the metal thin film that contains Cu and the photoresist. Therefore, if the insulating film or the metal film that does not contain Cu is formed on the metal thin film and the photoresist is formed thereon, the photoresist can be prevented from coming off.

"That is, according to the method described above, by sandwiching the insulating film or the metal film that does not contain Cu between the photoresist and the metal thin film, the following effect can be achieved: because the adhesion between the photoresist and the metal thin film to be etched is increased, partial deformation of a wiring pattern in forming the wiring can be reduced, and therefore, a wiring defect or the like that causes an increase of wiring resistance and a wiring disconnection can be eliminated.

"According to the method described above, even if the wet etching, which requires simpler equipment and process, is used to form the metal wiring, the metal wiring that is made of Cu can be formed in design dimensions. The metal thin film that contains Cu has a problem of very low etching speed when processed with dry etching by the RIE method, however, the above-mentioned method of the present invention employs the wet etching, which allows the metal thin film to be processed at an appropriate speed, and as a result, high productivity can be maintained.

"In order to solve the above-mentioned problems, in a method of manufacturing a semiconductor substrate, semiconductor elements and wiring are formed by patterning a gate electrode layer and a source electrode layer that contain Cu, employing the above method of forming the wiring.

"According to the above manufacturing method, when using a Cu conductive film as a wiring material, an effect in which the wiring can be formed to design width and height can be achieved.

"Effects of the Invention

"As described above, the method of forming wiring includes: depositing a metal thin film that contains Cu on a base member; forming an insulating film or a metal film that does not contain Cu on the metal thin film; patterning a photoresist by the photolithography on the insulating film or the metal film that does not contain Cu; etching the insulating film or the metal film that does not contain Cu by isotropic dry etching using the photoresist as an etching mask; and forming metal wiring by removing the photoresist after the insulating film or the metal film that does not contain Cu is etched, and etching the metal thin film by isotropic wet etching using the insulating film or the metal film that does not contain Cu as an etching mask so as to remove the metal thin film.

"According to the method described above, an effect in which metal wiring made of Cu can be formed to design dimensions can be achieved even when the wet etching, which can be performed with simpler equipment and process, is used in forming the metal wiring."

For additional information on this patent, see: Ohhira, Shinya. Method of Forming Wiring and Method of Manufacturing Semiconductor Substrates. U.S. Patent Number 8647980, filed February 17, 2011, and published online on February 11, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=63&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3107&f=G&l=50&co1=AND&d=PTXT&s1=20140211.PD.&OS=ISD/20140211&RS=ISD/20140211

Keywords for this news article include: Electronics, Semiconductor, Photolithography, Sharp Kabushiki Kaisha.

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Source: Electronics Newsweekly


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