The patent's inventor is Lee, Sang-Oh (Gyeonggi-do, KR).
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for fabricating a storage node (SN) of a semiconductor device.
"As the integration degree of semiconductor devices has increased, much research has been conducted to secure sufficient capacitance within a limited area. Accordingly, an SN is formed in a three-dimensional structure, for example, a cylindrical structure.
"FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
"Referring to FIG. 1A, an interlayer dielectric layer 12 is formed on a substrate 11 having a certain structure formed therein, and an SN contact plug 13 is formed through the interlayer dielectric layer 12. An etching stop layer 14 and an isolation layer 15 are formed on the interlayer dielectric layer 12. The isolation layer 15 and the etching stop layer 14 are selectively etched to form an open region 16 exposing the SN contact plug 13. The interlayer dielectric layer 12 and the isolation layer 15 may include an oxide layer, and the etching stop layer 14 may include a nitride layer.
"Referring to FIG. 1B, an SN 17 is formed in the open region 16, and a wet dip-out process is performed to remove the isolation layer 15. Although not illustrated in FIG. 113, a dielectric layer and a plate electrode may be sequentially formed to complete a capacitor.
"As the integration degree of the semiconductor devices increases, the critical dimension (CD) of the open region 16 in which the SN 17 is to be formed is continuously reduced. Accordingly, in the conventional method, it is difficult to secure a sufficient area in which the SN 17 is to be formed. As a result, the SN 17 may be formed abnormally.
"To address such a concern, the isolation layer 15 at the side of the open region 16 may be additionally etched to expand the CD of the open region 16, after the open region 16 is formed. However, etching the isolation layer 15 at the side of the open region 16 by a predetermined thickness through a general etching process (dry etching or wet etching) is a very difficult process. Therefore, it is not easy to realize the etching. Furthermore, when the isolation layer 15 at the side of the open region 16 is etched, a bridge may easily occur between the adjacent open regions 16. Accordingly, the adjacent SNs 17 may be short-circuited."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "An exemplary embodiment of the present invention is directed to a method for fabricating a semiconductor device, which is capable of stably expanding the CD of an open region.
"In accordance with an exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes forming an isolation layer over a substrate, forming a plurality of open regions exposing the substrate by selectively etching the isolation layer, performing a surface treatment over the isolation layer, expanding the open regions by removing the surface-treated portion of the isolation layer, and forming a conductive layer in the expanded open regions.
"In accordance with another exemplary embodiment of the present invention, a method for fabricating a semiconductor layer includes: forming an interlayer dielectric layer having a plurality of storage node contact plugs, forming an isolation layer over the interlayer dielectric layer, forming a plurality of open regions exposing the respective storage node contact plugs by selectively etching the isolation layer, performing a surface treatment over the isolation layer, expanding the open regions by removing the surface-treated portion of the isolation layer, forming a storage node in each of the expanded open regions, and removing the isolation layer."
For the URL and additional information on this patent, see: Lee, Sang-Oh. Method for Fabricating Semiconductor Device Having Expanded Critical Dimension by Performining Surface Treatment. U.S. Patent Number 8647958, filed
Keywords for this news article include: Treatment, Electronics,
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