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Patent Issued for Electrostatic Discharge (ESD) Device and Semiconductor Structure

February 26, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Wen, Yung-Ju (Taoyuan County, TW); Wang, Chang-Tzu (Taoyuan County, TW); Tang, Tien-Hao (Hsinchu, TW); Su, Kuan-Cheng (Taipei, TW), filed on November 7, 2011, was published online on February 11, 2014.

The assignee for this patent, patent number 8648421, is United Microelectronics Corp. (Hsinchu, TW).

Reporters obtained the following quote from the background information supplied by the inventors: "This invention relates to a semiconductor device, and more particularly relates to an electrostatic discharge (ESD) device and a semiconductor structure derived from it.

"For sufficient ESD robustness of the ESD devices in CMOS integrated circuits, a salicide (self-aligned silicide) blocking (SAB) layer can be disposed on the drain-side diffusion to block salicide formation thereon and thus prevent current localization and provide a ballast resistance to increase the current uniformity at the drain-side.

"FIG. 1 illustrates a layout of a series of conventional ESD devices with shared source/drain regions. Each ESD device includes a gate line 110 on a substrate 100, a source region 120 at one side of the gate line 110, a drain region 130 at the other side of 110 shared with another ESD device, a ring-shaped SAB layer 140 partially covering the drain region 130, a salicide layer 150 on the source region 120 and on the portions of the drain region 130 not covered by the SAB layer 140, contact plugs 160a on the salicide layer 150 on the source region 120, and contact plugs 160b on the salicide layer 150 on the drain region 130 surrounded by the SAB layer 140.

"However, in an advanced process forming high-k gate dielectric and metal gates, a SAB layer may not be present. Hence, a design that sustains high ESD robustness in fully salicided ESD devices is required. Though increasing the distance (D.sub.cg) between the gate line 110 and the nearest contact plugs 160b in the conventional ESD devices can prevent current localization and provide a larger ballast resistance to enhance the ESD robustness, the area of drain-side diffusion or the ESD device is much increased."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Accordingly, this invention provides ESD device that has higher ESD robustness without increasing the device dimension.

"This invention also provides a semiconductor structure that is derived from the ESD device of this invention.

"The ESD device of this invention includes a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having a plurality of comb-teeth parts, a salicide layer on the source and drain regions, and a plurality of contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at the tip portion thereof, at least one of the contact plugs.

"The semiconductor structure of this invention includes two above ESD devices of this invention that are arranged in a complementary manner, in which the two comb-shaped drain regions of the two ESD devices face each other, the comb-teeth parts of the first drain region and those of the second drain region are arranged alternately, and the comb-teeth parts of the first drain region are separated from those of the second drain region by a device isolation layer.

"In some embodiments, the above ESD device or semiconductor structure further includes a salicide block (SAB) layer covering a portion of each comb-teeth part of the drain region(s), wherein the salicide layer is not disposed on the portions of the comb-teeth parts covered by the SAB layer.

"Since the drain region has a comb shape and the contact plugs of the drain region are disposed at the tip portion of the comb-teeth parts of the comb-shaped drain region in the ESD device of this invention, the distance (D.sub.cg) between the gate line and the contact plugs is much increased as illustrated later. Therefore, even when a SAB layer is absent, current localization still can be effectively prevented and a sufficient ballast resistance can be provided to enhance the ESD robustness.

"In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below."

For more information, see this patent: Wen, Yung-Ju; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cheng. Electrostatic Discharge (ESD) Device and Semiconductor Structure. U.S. Patent Number 8648421, filed November 7, 2011, and published online on February 11, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=54&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2669&f=G&l=50&co1=AND&d=PTXT&s1=20140211.PD.&OS=ISD/20140211&RS=ISD/20140211

Keywords for this news article include: Semiconductor, United Microelectronics Corp.

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Source: Electronics Newsweekly


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