The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "In a typical flip-chip electronic package, an integrated circuit (IC) chip (also referred to as a die) is joined to a substrate through a series of solder connections. The substrate is typically a ceramic or organic laminate, and the solder connections may comprise controlled collapse chip connection (C4) bumps. An underfill material is provided in the space between the chip and the substrate and encapsulating the solder connections. The underfill is usually an epoxy resin and commonly includes inorganic fillers such as silica.
"A common problem with flip-chip packages is delamination of various layers of the package. For example, delamination of the underfill from the chip can result from mismatched coefficients of thermal expansion (CTE) between the respective materials of the package. When the package is raised to an elevated temperature, e.g., during thermal cycling testing or field operation (actual use), the mismatched CTE's can produce thermally-induced mechanical stress within the package, which can lead to delaminating, cracking, and electronic failure of the chip.
"In light of the delaminating, and for development and manufacturing troubleshooting purposes, it is desirable to have a method to rapidly predict the adhesion reliability of the underfill to the chip in thermal cycling testing or field operation. Some adhesion tests are performed using underfill material adhered to a surface similar to that used in a package. However, these tests do not utilize an actually manufactured IC module, and thus do not accurately measure the adhesion of the underfill as it is affected by aspects of the manufacturing processes. As a result, these tests do not show good correlation with the actual reliability of the packages, due to differences with the geometry and process conditions between the manufactured modules and laboratory experiments. Other adhesion tests do utilize a manufactured module, but are performed at a macroscopic scale, e.g., shearing an entire chip off of the laminate. Such macroscopic tests do not isolate the adhesion of the underfill, and instead measure the adhesion of the entire interface between the chip and laminate including the adhesion at the solder connections.
"Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In a first aspect of the invention, there is a method that includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.
"In another aspect of the invention, there is a method to determine an adhesion force of an underfill material to a surface in a flip-chip module. The method includes forming trenches in the underfill material, wherein the trenches create at least one free-standing block of the underfill material adhered to the surface. The method also includes pressing a blade against a wall of the at least one block until the at least one block dislocates from the surface. The method additionally includes measuring a force applied by the blade during the dislocating of the at least one block from the surface.
"In yet another aspect of the invention, there is a method comprising measuring adhesion of an underfill material to a chip at a plurality of locations on the chip, wherein the underfill material and the chip are included in a manufactured module.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
"FIGS. 1-6 show a module and processing steps in accordance with aspects of the invention; and
"FIG. 7 shows a flow diagram of a method in accordance with aspects of the invention."
For additional information on this patent application, see: CADOTTE, Maxime; PAQUET, Marie-Claude; SYLVESTRE,
Keywords for this news article include:
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