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Researchers Submit Patent Application, "Multilayer Type Coreless Substrate and Method of Manufacturing the Same", for Approval

February 19, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Kim, Ki Hwan (Gyunggi-do, KR); Kang, Myung Sam (Gyunggi-do, KR); Sohn, Keung Jin (Gyunggi-do, KR); Oh, Yoong (Gyunggi-do, KR); Kim, Da Hee (Gyunggi-do, KR); Yoo, Ki Young (Gyunggi-do, KR); Lee, Han Ui (Gyunggi-do, KR); Oh, Sang Hyuck (Gyunggi-do, KR), filed on October 30, 2012, was made available online on February 6, 2014.

The patent's assignee is Samsung Electro-Mechanics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a multilayer type coreless substrate and a method of manufacturing the same.

"Generally, a printed circuit board is implemented by wiring a copper foil on one surface or both surfaces of a board made of various kinds of thermosetting synthetic resins, fixedly disposing integrated circuits (ICs) or electronic components on the board, and implementing electrical wirings therebetween and then coating the electrical wirings with an insulator.

"In accordance with the recent development of electronic industries, a demand for multi-functional and light and small electronic components has been rapidly increased. Therefore, there is a need to increase a wiring density of a printed circuit board on which the electronic components are mounted and reduce a thickness thereof.

"In particular, in order to cope with the thinness of the printed circuit board, a coreless substrate with the reduced thickness and signal processing time by removing a core substrate has been spotlighted. In case of the coreless substrate, since the core substrate is removed, a carrier member serving as a support during a manufacturing process is required. Buildup layers including circuit layers and insulating layers are formed on both surfaces of the carrier member by a general method of manufacturing a substrate and the carrier member is removed to separate upper and lower substrates from each other, such that the coreless substrate is completed.

"As described in Korean Patent Laid-Open Publication No. 2010-0043547 (published on Apr. 29, 2010), in a method of manufacturing a coreless substrate according to the prior art, a laser direct ablation (LDA) method has been performed in order to form opening parts in an insulating layer before forming vias for electrical connection between the respective buildup layers.

"However, the LDA method has caused an increase in machining time due to a limitation of a laser spot size when a size of the opening part is large.

"Further, in the method of manufacturing a coreless substrate according to the prior art, since laser machining should be performed several times, a process was complicated and a cost has increased."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention has been made in an effort to provide a multilayer type coreless substrate in which a plurality of insulating layers including pillars for electrical connection formed by a patterning process using a dry film are laminated.

"Further, the present invention has been made in an effort to provide a method of manufacturing a multilayer type coreless substrate in which a plurality of insulating layers including pillars for electrical connection are laminated.

"According to a preferred embodiment of the present invention, there is provided a multilayer type coreless substrate including: a first insulating layer including at least one first pillar; a plurality of insulating layers each laminated in directions of both surfaces of the first insulating layer and each including at least one circuit layer and at least one other pillar connected to the circuit layer; and a plurality of outermost circuit layers each contacting pillars included in outermost insulating layers among the plurality of insulating layers and disposed on outer surfaces of the outermost insulating layers, wherein the circuit layers and other pillars formed on the directions of both surfaces of the first insulating layer, respectively, are disposed symmetrically to each other based on the first insulating layer.

"The circuit layers and other pillars may be sequentially laminated in directions of both surfaces based on the first pillar of the first insulating layer, respectively, and may be disposed symmetrically to each other based on the first pillar.

"The outermost circuit layer may include a first or second surface treating film formed thereon.

"The first surface treating film may be any one of an organic solderability preservative (OSP) treating film, a black oxide film, and a brown oxide film, instead of a solder resist (SR).

"The second surface treating film may be any one of a gold plating film, an electro gold plating film, an electroless gold plating film, and an electroless nickel immersion gold (ENIG) plating film.

"According to another preferred embodiment of the present invention, there is provided a method of manufacturing a multilayer type coreless substrate, the method including: (A) preparing a carrier substrate including at least one copper foil formed on one surface or both surfaces of an insulating surface; (B) forming a coreless printed circuit precursor on one surface or both surfaces of the carrier substrate; (C) separating the carrier substrate; (D) performing a polishing cutting process on the coreless printed circuit precursor; and (E) laminating a plurality of other insulating layers on an outer surface of the coreless printed circuit precursor, the plurality of other insulating layers sequentially including other circuit layers and other pillars.

"The method may further include: (F) forming outermost circuit layers at outermost insulating layers among other insulating layers; and (G) forming a first or second surface treating film on the outermost circuit layers.

"The first surface treating film may be any one of an OSP treating film, a black oxide film, and a brown oxide film, instead of an SR, and the second surface treating film may be any one of a gold plating film, an electro gold plating film, an electroless gold plating film, and an ENIG plating film.

"Step (B) may include: (B-1) forming a plurality of first pillars by filling a first dry film pattern disposed on one surface or both surfaces of the carrier substrate with copper; (B-2) delaminating the first dry film pattern; (B-3) forming a first insulating layer on one surface or both surfaces of the carrier substrate so as to bury the first pillars therein; (B-4) performing a polishing cutting process on the first insulating layer so as to expose the first pillars; (B-5) forming a dry film pattern for forming a first circuit layer on an outer surface of the first insulating layer exposing the first pillars; (B-6) forming the first circuit layer by filling the dry film pattern for forming the first circuit layer with copper and delaminating the dry film pattern for forming the first circuit layer; (B-7) forming a second dry film pattern on the outer surface of the first insulating layer including the first circuit layer; (B-8) forming second pillars connected to the first circuit layer by filling the second dry film pattern with copper and delaminating the second dry film pattern; and (B-9) forming a second insulating layer so as to bury the second pillars therein.

"Steps (B-1), (B-6), and (B-8), the copper may be filled by any one of a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a subtractive method, an additive method using electroless copper plating or electro copper plating, a semi-additive process (SAP), and a modified semi-additive process (MSAP).

"In steps (B-1), (B-6), and (B-8), the copper may be filled by a sputtering method.

"In step (C), the carrier substrate may include an insulating plate; at least two copper foils laminated on one surface or both surfaces of the insulating plate; and a release layer disposed between the copper foils and may be routed and separated using the release layer.

"Step (D) may be performed by using any one of a belt-sander, an end-mill, or a ceramic buff, and a chemical mechanical polishing (CMP) process.

"Step (E) may include: (E-1) forming other circuit layers on the flat outer surface; (E-2) forming dry film patterns for forming other pillars on the flat outer surface including other circuit layers formed thereon; (E-3) forming other pillars connected to other circuit layers by filling the dry film patterns for forming other pillars with copper; (E-4) delaminating the dry film patterns for forming other pillars; (E-5) laminating other insulating layers so as to bury other pillars; and (E-6) polishing and cutting other insulating layers so as to expose other pillars, and steps (E-1) to (E-6) may be repeatedly performed.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

"FIG. 1 is a cross-sectional view of a multilayer type coreless substrate according to a first preferred embodiment of the present invention;

"FIGS. 2A to 2L are process views sequentially showing a method of manufacturing a multilayer type coreless substrate according to the first preferred embodiment of the present invention; and

"FIGS. 3A to 3D are process views sequentially showing a method of manufacturing a multilayer type coreless substrate according to a second preferred embodiment of the present invention."

For additional information on this patent application, see: Kim, Ki Hwan; Kang, Myung Sam; Sohn, Keung Jin; Oh, Yoong; Kim, Da Hee; Yoo, Ki Young; Lee, Han Ui; Oh, Sang Hyuck. Multilayer Type Coreless Substrate and Method of Manufacturing the Same. Filed October 30, 2012 and posted February 6, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6232&p=125&f=G&l=50&d=PG01&S1=20140130.PD.&OS=PD/20140130&RS=PD/20140130

Keywords for this news article include: Circuit Board, Electronic Components, Samsung Electro-Mechanics Co. Ltd.

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Source: Electronics Newsweekly


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