The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
"In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into an active phase and a precharge phase, with the active phase being used to read or write one or more memory cells of the array and the precharge phase being used to precharge the bitlines to a precharge voltage in preparation for the next cycle. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
"For a given read or write operation, the corresponding memory cycle is more particularly referred to as a read cycle or a write cycle, respectively. In certain types of memory devices, such as static random access memories (SRAMs), the read and write cycle times are not equal. The read access time is typically longer than the write access time, while the write precharge time is longer than the read precharge time.
"As is well known to those skilled in the art, read and write self-time tracking arrangements may be used in order to establish appropriate signal timing for respective read and write operations. Such self-time tracking functionality is often designed to control the read and write signal timing over expected process, voltage and temperature (PVT) variations. This is particularly important for high-speed operations having read and write cycle frequencies in the gigahertz (GHz) range.
"A conventional self-time tracking arrangement of this type utilizes a dummy row of memory cells and a dummy column of memory cells, associated with a dummy wordline and a dummy bitline, respectively, with those memory cells being configured in substantially the same manner as the actual memory cells of the memory array. A dummy wordline driver generates a dummy wordline signal for application to the dummy wordline with substantially the same timing as an actual wordline signal applied to an actual wordline of the memory array. The dummy wordline and dummy bitline are also known as a self-time wordline (STWL) and a self-time bitline (STBL), respectively.
"In order to permit independent control of the read and write cycle times, self-time tracking circuitry may be separated into two paths, one for read and another for write. This approach is also called dual mode self-time (DMST).
"Conventional approaches to reading data from a memory cell include the use of differential sense amplifiers. In a typical conventional arrangement, sense amplifiers are associated with respective columns of the memory array. For each read memory cycle, the sense amplifier is turned on in order to sense data on a corresponding bitline, and then turned off once the sensed data is latched at the sense amplifier output. The sense amplifier is turned on and off responsive to respective logic states of a sense amplifier enable signal. The turning on and turning off of the sense amplifier is also referred to as enabling and disabling the sense amplifier. The use of differential sense amplifiers generally provides faster sensing with lower dynamic power consumption than single-ended sensing arrangements.
"However, controlling the timing of the transitions in the sense amplifier enable signal can be problematic, particularly for high-speed read operations. For example, in conventional arrangements, the sense amplifier enable signal may be provided by a sense latch, with the sense latch being set and reset in order to turn on and turn off the sense amplifiers. More particularly, the sense latch may be reset responsive to a pulse of a sense off signal that corresponds to a delayed and inverted version of the sense amplifier enable signal, as returned to the sense latch from a final one of the sense amplifiers. It can be very difficult to accurately control the delay of the sense off signal, particularly over PVT variations. As a result, read memory cycle time is increased, thereby degrading memory access time performance."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Illustrative embodiments of the invention provide a memory device in which separate sense amplifier control signals are generated for respective sense amplifiers of the memory device. This allows more accurate control of the sense amplifier timing over PVT variations, thereby facilitating high-speed read operations.
"In one embodiment, a memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.
"By way of example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell.
"A given one of the logic gates may comprise a first input coupled to the bitline of the dummy memory cell, a second input adapted to receive a read mode signal, and an output coupled to the control input of the given sense amplifier. More particularly, the logic gate may comprise a NOR gate, with the read mode signal comprising a complementary read mode signal having a logic low level indicative of a read operation being performed and a logic high level indicative of a read operation not being performed.
"The control circuitry may further comprise signal generation circuitry having an output coupled to the dummy wordline and providing a dummy wordline signal to the dummy wordline for controlling discharge of dummy bitlines associated with the dummy memory cells.
"One or more of the illustrative embodiments can provide a memory device that exhibits shorter read memory cycles and lower power consumption, as well as improved overall operating performance, relative to conventional devices.
"A memory device in accordance with embodiments of the invention may be implemented, for example, as a stand-alone memory device, such as a packaged integrated circuit, or as an embedded memory in a microprocessor or other processing device.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a block diagram of a semiconductor memory device comprising a memory array having a plurality of memory cells and incorporating control circuitry that generates separate control signals for respective sense amplifiers in an illustrative embodiment of the invention.
"FIG. 2 shows a more detailed view of a portion of the FIG. 1 memory device in an illustrative embodiment.
"FIG. 3 is a timing diagram illustrating the operation of the FIG. 2 circuitry.
"FIG. 4 shows a more detailed view of a portion of the FIG. 2 circuitry including a dummy memory cell and an associated sense amplifier.
"FIG. 5 is a timing diagram illustrating the operation of the FIG. 4 circuitry.
"FIG. 6 is a block diagram of a processing device which incorporates the memory device of FIG. 1.
"FIG. 7 is a block diagram of a processor integrated circuit which incorporates the memory device of FIG. 1 as an embedded memory."
For additional information on this patent application, see: Trivedi, Manish; Rao, Setti Shanmukheswara; Goel,
Keywords for this news article include: Electronics, Semiconductor,
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