The assignee for this patent, patent number 8642997, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to semiconductor devices, and more particularly to devices with a gate structure with reduced gate resistance and methods for fabricating the same.
"Conventional top-gated field effect transistors (FET) include a number of associated parasitics. With continuous gate-length scaling associated with denser device layouts, FET gate resistance increases. As a result, maximum oscillating frequency (f.sub.MAX) performance of complementary metal oxide semiconductor (CMOS) FETs has improved little beyond the 45 nm node. With conventional CMOS fabrication techniques, gate resistance can only be reduced by using multiple fingers, decreasing device width or employing a double-contacted gate structure. In such devices, additional metal layers (with lower resistance than poly-silicon) can make contact with a gate node only outside of the device area to reduce parasitic capacitances to make the device operable.
"Top-gated devices may include a mushroom gate structure having an upper portion that extends over adjacent active regions. The mushroom-like gate structure attempts to reduce gate resistance by adding material to the gate electrode, but may in some instances contribute to capacitance parasitics with surrounding metal structures."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer.
"Another device with reduced gate resistance includes a first dielectric layer having a first conductive portion embedded therein. A second dielectric layer is formed over the first dielectric layer and a portion of the first conductive portion. A second conductive portion is formed on the first conductive portion and is electrically connected to the first conductive portion and is formed within the second dielectric layer such that the first conductive portion extends laterally beyond the second conductive portion in at least one direction. A channel layer is provided over the second conductive portion, and source and drain electrodes are formed on opposite end portions of a channel region of the channel layer.
"A method for forming a device with reduced gate resistance includes forming a conductive sheet in a first dielectric material; depositing a second dielectric material on the first dielectric material and the conductive sheet; forming one or more openings in the second dielectric material down to the conductive sheet; forming one or more conductive fingers in the one more openings in contact with the conductive sheet to form an embedded gate structure; depositing a gate dielectric layer on the one or more conductive fingers; forming a channel layer on the gate dielectric layer; and forming source and drain electrodes at end portions of a channel region of the channel layer.
"These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings."
For more information, see this patent: Han, Shu-Jen;
Keywords for this news article include: Electronics, Semiconductor,
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