News Column

Patent Issued for Strapped Dual-Gate VDMOS Device

February 19, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Alberhasky, Scott J. (Portland, OR); Hart, David E. (Cornelius, OR); Uppili, Sudarsan (Portland, OR), filed on September 30, 2011, was published online on February 4, 2014.

The patent's assignee for patent number 8643067 is Maxim Integrated Products, Inc. (San Jose, CA).

News editors obtained the following quote from the background information supplied by the inventors: "Power metal-oxide-semiconductor field-effect transistor (MOSFET) devices, such as vertical diffused metal oxide semiconductor (VDMOS) devices, are used in power application devices because they complement both bipolar devices and complementary metal-oxide-semiconductor CMOS devices through bi-polar-CMOS-DMOS (BCD) processes. For example, VDMOS devices may be used in power supplies, buck converters, and low voltage motor controllers to furnish power application functionality.

"The on-state resistance ('R.sub.ON'), the maximum breakdown voltage ('BV.sub.DSS'), and the overall capacitances of the device are important characteristics of VDMOS designs. These characteristics are important operating parameters of the VDMOS devices, which dictate the applications with which the devices may be utilized. On-state resistance is usually dependent upon the design and layout of the device, the process condition, temperature, drift region length, doping concentration of the drift region, and the various materials used to fabricate the devices. Breakdown voltage is defined as the largest reverse voltage that can be applied to the drain of the transistor without causing an exponential increase in the current. Moreover, various parasitic capacitances in the devices lead to reduced operating frequency."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Semiconductor devices, such as VDMOS devices, are described that include a strapped dual-gate configuration to reduce the gate to drain capacitance (C.sub.gd) of the devices. In one or more implementations, the semiconductor devices include a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes a first and second body region formed proximal to the first surface. Each body region includes a source region formed therein. The semiconductor substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the semiconductor substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower an effective resistance of the dual-gate.

"This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter."

For additional information on this patent, see: Alberhasky, Scott J.; Hart, David E.; Uppili, Sudarsan. Strapped Dual-Gate VDMOS Device. U.S. Patent Number 8643067, filed September 30, 2011, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=71&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3542&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: Electronics, Semiconductor, Maxim Integrated Products Inc..

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Source: Electronics Newsweekly


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