Patent number 8642461 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "An ever present objective of semiconductor assembly is to provide packages for enclosing/encasing semiconductor components that are smaller, thinner, cooler, and less expensive to manufacture at a high rate of production. One type of semiconductor package is the Plastic Dual In-line Package (PDIP). Another type of semiconductor package is the gull-wing Small Outline (SO) package. These semiconductor packages generally include leads (connectors) extending from the sides of the package. Other types of semiconductor packages are flat lead-less packages, such as Dual Flat No-leads (DFN) and Quad Flat No-leads (QFN) packages. A DFN package has lead lands on only two sides of the perimeter of the package bottom, while a QFN package has lead lands on four sides of the package bottom. Some DFN and QFN package sizes can range from one millimeter by two millimeter (1.times.2 mm) packages having three (3) lead lands, to ten millimeter by ten millimeter (10.times.10 mm) packages having sixty-eight (68) lead lands.
"Because the lead-frame is on the bottom of the package, flat no-lead packages can provide superior thermal performance when compared to leaded packages having similar body size and lead counts. Further, in a flat no-leads configuration, the die-attach-pad can be exposed on the bottom exterior of the package, allowing it to be soldered directly to a printed circuit board, and providing a direct route for heat to dissipate away from the package. The exposed die-attach-pad, often referred to as an exposed thermal pad, may greatly improve heat transfer out of the integrated circuit package and into the printed circuit board. However, when multiple flat no-lead packages are manufactured together and then separated from one another (singulated), it may be difficult to obtain good solder connections to lead lands located on side flanks of an IC package, because these side portions are not coated with solder wettable material prior to singulation. Further, it may be difficult to inspect solder connections to the lead lands using visual inspection techniques."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Techniques for providing a semiconductor chip package with side wettable plating are disclosed. In one or more implementations, the techniques may include singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and electrolytically plating the lead land of the semiconductor chip package.
"This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter."
URL and more information on this patent, see: Huening, Kenneth J.. Side Wettable Plating for Semiconductor Chip Package. U.S. Patent Number 8642461, filed
Keywords for this news article include: Electronics, Circuit Board, Semiconductor,
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