Patent number 8642471 is assigned to The institute of Microelectronics,
The following quote was obtained by the news editors from the background information supplied by the inventors: "The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a kind of transistor that is widely applied in digital circuits and analog circuits. When the gate dielectric layer of a MOSFET is made of a high-k dielectric material, the gate drain current shall be effectively reduced; however, as a high-k gate dielectric layer is formed at first, the molecular structure of the high-k gate dielectric layer probably have defects. In order to remove the defects, it has to be annealed at a high temperature (600.degree. C.-800.degree. C.). Besides, annealing a high-k gate dielectric layer is able to enhance reliability of a transistor. However, a metal silicide layer in the transistor cannot endure the high temperature required for annealing the high-k dielectric layer, wherein the structure of the metal silicide layer is prone to change under the high temperature, such that the resistivity of the metal silicide layer increases, which thereby impedes performance of the transistor.
"In the prior art, patent application US2007/0141798A1 provides a method capable of annealing a high-k gate dielectric layer without damaging a metal silicide layer, which comprises following steps:
"forming a transistor with a sacrifice gate on a substrate; depositing a first interlayer dielectric layer on the substrate; removing the sacrifice gate to form a gate trench; depositing a high-k dielectric layer in the gate trench; annealing the high-k dielectric layer; depositing a first metal layer in the gate trench; depositing a second interlayer dielectric layer on the first interlayer dielectric layer and the transistor; etching the first interlayer dielectric layer and the second interlayer dielectric layer to a source and a drain to form a first contact trench and a second contact trench respectively; depositing a second metal layer into the first contact trench and the second contact trench; annealing the second metal layer to form a metal silicide layer at the source and the drain; and depositing a third metal layer to fill the first contact trench and the second contact trench.
"Since a contact layer (e.g. a metal silicide layer) is formed after the high-k dielectric layer has been annealed, thus the metal silicide layer is prevented from damage under the high temperature.
"However, aforesaid method though is able to protect the metal silicide layer from damage arising from annealing of the high-k dielectric layer, limitations of the method lies in that the metal silicide layer is formed nowhere but between the contact trench and the source/drain regions, thus the area of the region covered by metal silicide on the surface of the source/drain regions is limited, thus the contact resistance between the source/drain regions and the metal silicide layer of the transistor cannot be reduced adequately. Therefore, how to reduce the contact resistance between the source/drain regions and the contact layer (e.g. a metal silicide layer) becomes an issue urgent to solve."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The present invention aims to provide a semiconductor structure and a method for manufacturing the same, which are favorable for reducing the contact resistance between source/drain regions and a contact layer (e.g. a metal silicide layer).
"In one aspect, the present invention provides a method for manufacturing a semiconductor structure, which comprises following steps:
"a) providing a substrate, and forming a dummy gate stack on the substrate, sidewall spacers on sidewalls of the dummy gate stack, and source/drain regions at both sides of the dummy gate stack, wherein the dummy gate stack comprises a dummy gate;
"b) forming a first contact layer on surfaces of the source/drain regions;
"c) forming an interlayer dielectric layer to cover the first contact layer;
"d) removing the dummy gate or the dummy gate stack to form an opening, filling the opening with a first conductive material or with a gate dielectric layer and a first conductive material so as to form a gate stack structure;
"e) forming through holes within the interlayer dielectric layer, so that a portion of the first contact layer or a portion of the first contact layer and the source/drain regions are exposed in the through holes;
"f) forming a second contact layer on the exposed portions;
"g) filling the through holes with a second conductive material to form contact vias.
"In another aspect, the present invention further provides a semiconductor structure, comprising a substrate, source/drain regions, a gate stack structure, an interlayer dielectric layer and contact vias;
"the gate stack structure is formed on the substrate and comprises a gate dielectric layer and a gate;
"the source/drain regions are formed within the substrate and positioned at both sides of the gate stack structure;
"the interlayer dielectric layer covers the source/drain regions;
"the contact vias comprises a second conductive material embedded into the interlayer dielectric layer and electrically connected with the source/drain regions, wherein:
"a first contact layer is formed between the interlayer dielectric layer and the source/drain regions; and
"a second contact layer is formed between the contact vias and the source/drain regions.
"As compared to the prior art, the present invention exhibits following advantages:
"1) the area of a region covered by a contact layer on the surface of the source/drain regions may be increased by way of forming a first contact layer on the surface of the source/drain regions and forming a second contact layer on the first contact layer exposed by through holes or on the first contact layer and a portion of the surface of the source/drain regions, and it is thence favorable for reducing the contact resistance between the source/drain regions and the contact layer (e.g. a metal silicide layer);
"2) the first contact layer exhibits thermal stability under the temperature required for annealing at formation of a gate stack structure, thus it is able to maintain a low resistance under a rather high temperature for annealing (e.g. 850.degree. C.), therefore, the subsequent processes may be performed under a high temperature without impeding performance of the semiconductor structure;
"3) the formation of the first contact layer is favorable for restraining generation of piping defect so as to reduce occurrence of short circuits in the semiconductor structure."
URL and more information on this patent, see: Yin, Haizhou; Luo, Jun; Zhu, Huilong; Luo, Zhijiong. Semiconductor Structure and Method for Manufacturing the Same. U.S. Patent Number 8642471, filed
Keywords for this news article include: Semiconductor, The institute of
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