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Patent Issued for Semiconductor Device with Buried Bit Line and Method for Fabricating the Same

February 19, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Hwang, Eui-Seong (Gyeonggi-do, KR), filed on July 20, 2012, was published online on February 4, 2014.

The assignee for this patent, patent number 8643096, is SK Hynix Inc. (Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to a semiconductor device fabricating technology, and more particularly, to a semiconductor device with buried bit lines and a method for fabricating the same.

"As the degree of integration of a semiconductor memory device has increased, in order to reduce a plane area occupied by a unit cell, a cell structure has been changed from 8F.sup.2 and 6F.sup.2 to 4F.sup.2 (F.sup.2: cell size factor). Various methods for forming other component elements such as transistors, bit lines, word lines, capacitors, etc. in step with such reduction in the area of the unit cell have been suggested. In particular, in order to realize a 4F.sup.2 cell structure, a vertical channel semiconductor device has been proposed, in which a source and a drain are disposed up and down to induce a vertical channel.

"In the vertical channel semiconductor device, a gate electrode is formed around an active pillar which vertically extends from the main surface of a substrate and a source and a drain are formed in the upper and lower parts of the active pillar with the gate electrode disposed therebetween, by which a channel is vertically formed from the main surface of the substrate. Accordingly, even when the area of the semiconductor device is reduced, a channel length may not be adversely influenced.

"In realizing the vertical channel semiconductor device in this way, a buried bit line structure has been disclosed, in which a bit line is buried under an active pillar.

"In the conventional art, a buried bit line is formed in such a way that impurity ions are implanted into a substrate between active pillars to form an impurity region and the substrate is etched between the active pillars to separate the impurity region. However, the resistance of the buried bit line may increase due to limitations in the doping concentration of the impurity.

"Although the resistance of the buried bit line may be reduced by forming the buried bit line using a metallic layer with low resistance, it may be difficult to apply such a method in terms of a structural aspect. For instance, in order to use a metal as a buried bit line, a method has been suggested, in which a buried bit line is formed by forming a contact (so called a one side contact: OSC) in such a way as to expose one sidewall of an active pillar. Nevertheless, the buried bit line with the OSC structure may have a complicated fabrication procedure, and require high difficulty fabricating technologies, and thus, it may be not easy to adapt the method for mass production."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Exemplary Embodiments of the present invention are directed to a semiconductor device with buried bit lines and a method for fabricating the same.

"In accordance with an exemplary embodiment of the present invention, a semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer are stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

"In accordance with another exemplary embodiment of the present invention, a semiconductor device includes a first structure including first trenches which are defined in a substrate, buried bit lines which partially fill the first trenches, and a first source/drain layer which fills remaining portions of the first trenches on the buried bit lines, and a second structure including stack patterns having a channel layer and a second source/drain layer are stacked therein, second trenches which expose sidewalls of the channel layer, word lines which are filled in the second trenches and a dielectric layer which gap-fills spaces between the word lines, wherein the buried bit lines and the word lines cross with each other, and the first source/drain layer and the channel layer contact with each other.

"In accordance with yet another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes defining trenches in a substrate forming buried bit lines to partially fill the trenches forming a first source/drain layer to fill remaining portions of the trenches on the buried bit lines sequentially forming a second source/drain layer and a channel layer on an entire surface of a sacrificial substrate, bonding the substrate and the sacrificial substrate with each other for the first source/drain layer and the channel layer to face each other, removing the sacrificial substrate, forming stack patterns by selectively etching the second source/drain layer and the channel layer for the etched channel layer to contact with the first source/drain layer, and forming word lines to cross with the buried bit lines and be disposed adjacent to sidewalls of the channel layer.

"In accordance with still another exemplary embodiment of the present invention, a method for fabricating a semiconductor device includes defining first trenches in a substrate, forming buried bit lines to partially fill the first trenches, forming a first source/drain layer to fill remaining portions of the first trenches on the buried bit lines, forming stack patterns having a second source/drain layer and a channel layer are stacked therein on a sacrificial substrate, forming a dielectric layer on the sacrificial substrate to fill spaces between the stack patterns and have second trenches which expose sidewalls of the channel layer; forming word lines to fill the second trenches, bonding the substrate and the sacrificial substrate with each other, wherein the buried bit lines and the word lines cross with each other and the first source/drain layer and the channel layer face each other, and removing the sacrificial substrate.

"According to the exemplary embodiments of the present invention, since other structures (for example, a channel layer and word lines) are bonded to a substrate in which buried bit lines are formed, low resistance buried bit lines may be easily realized, and the capacitance between adjacent buried bit lines may be reduced.

"Furthermore, according to the exemplary embodiments of the present invention, because a plurality of component elements constituting a vertical channel semiconductor device are separately fabricated on individual substrates and then the individual substrates are bonded with each other, structures may be simple, whereby it may be easy to increase the degree of integration, processes may be simplified, processing difficulties may be lessened, and applicability for mass production may be improved."

For more information, see this patent: Hwang, Eui-Seong. Semiconductor Device with Buried Bit Line and Method for Fabricating the Same. U.S. Patent Number 8643096, filed July 20, 2012, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=71&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3513&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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