News Column

Patent Issued for Scaleable Look-Up Table Based Memory

February 19, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Pan, Philip (Fremont, CA); Lee, Andy L. (San Jose, CA); Zhou, Lu (Santa Clara, CA); Kadkol, Aniket (Mountain View, CA), filed on October 20, 2011, was published online on February 4, 2014.

The patent's assignee for patent number 8644100 is Altera Corporation (San Jose, CA).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to the field of integrated circuits and in particular to programmable devices having convertible storage elements. In programmable devices, such as programmable logic devices (PLD), one type of random access memory is used to store configuration data of the PLD, this type of memory is often referred to as a configuration random access memory (CRAM). Each CRAM stores a pre-defined bit or information for a static task. Depending on the combination of multiple CRAMs, a PLD is able to work differently by using the same hardware. One skilled in the art will appreciate that the CRAM is loaded during the start-up operation of the PLD. The start-up operation where the CRAM is loaded, which may be referred to as a configuration mode, typically occurs between the chip power on and the user operation. Once the CRAM is loaded, the contents cannot be changed.

"Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic device, and at the same time, to provide greater flexibility. There is also a need to provide higher performance user memories also. Currently, the memories for a programmable logic device are typically pre-defined in size and these pre-defined memories are used under restrictions. Thus, the restrictions limit the flexibility of using the memories, e.g., when a portion of the programmable logic device that contains the memory, or combinational logic that includes memory is unused, the memory remains unused.

"Accordingly, there is a need for a highly flexible memory, which may be selectively configured between combinational logic functions and memory functions within a programmable logic device."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Embodiments of the present invention provide a method and a framework for configuring the memories within a programmable logic device to meet customer demands for greater flexibility. It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method on a computer readable medium. Several inventive embodiments of the present invention are described below.

"In one aspect of the invention, an integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM). The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM.

"In another aspect, a method for selectively configuring memory elements of a memory array of an integrated circuit is provided. The method includes providing first and second pairs of data lines into each row of the memory array. Data from either the first or second pairs of data lines is selected for accessing corresponding bit lines of a row of the memory array. An error check is performed through one of the data lines of the first pair of data lines for data accessing the memory array.

"Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention."

For additional information on this patent, see: Pan, Philip; Lee, Andy L.; Zhou, Lu; Kadkol, Aniket. Scaleable Look-Up Table Based Memory. U.S. Patent Number 8644100, filed October 20, 2011, and published online on February 4, 2014. Patent URL:

Keywords for this news article include: Electronics, Altera Corporation, Random Access Memory, Programmable Logic Device.

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Source: Electronics Newsweekly

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