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Patent Issued for PFC with High Efficiency at Low Load

February 19, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Pansier, Frans (Nuenen, NL), filed on January 14, 2010, was published online on February 4, 2014.

The patent's assignee for patent number 8644041 is NXP B.V. (Eindhoven, NL).

News editors obtained the following quote from the background information supplied by the inventors: "Power supplies for electronic devices such as televisions, personal computers (PCs), audio equipment, and personal digital assistants frequently are required to supply DC output power. Increasingly for such applications switched mode power supplies (SMPS) are used. SMPS require a DC input bus voltage, which conventionally is provided by rectifying an AC supply such as a mains supply. However, since rectification is highly non-linear, it produces a high levels of harmonics, and results in a significant degradation of the power factor of the supply. The power factor is the ratio of the real power to the apparent power of the system.

"As a result, it is increasingly common to include in power supplies such as SMPS, an input stage to operate as a power factor correction (PFC) stage.

"Such PFC stages are useful in ensuring compliance of the application with legal requirements for the control of harmonic components, such as the European Union's regulation EN61000-3-2. They also can be beneficial in ensuring that the application is compliant with minimum power factor requirements such as the mandatory at least 90% power factor for PC supplies under the European Commission's '80+' directive.

"In addition to being useful for or required by regulatory purposes, PFCs can be of benefit to the system designer, since they can be capable of providing a single bus voltage from universal mains voltages. Such a feature can be of value, in particular, for devices such as power supplies for laptops which can thereby automatically adjust for varying mains voltages, ranging from for example 100V in Japan to 240 in the UK. Moreover, a subsequent DC/DC converter stages can then be optimised for the specific bus voltage, which can result in either decreased costs or increased efficiencies or both.

"Under light load conditions, where the load is less than say 50% of its normal level, a two-stage architecture having a PFC upstream of a DC/DC converter, typically suffers a considerable degradation in efficiency. This is particularly significant for very light loads such as between 1% and 5%, or 5% to 10% of the normal level. Such loads can frequently be encountered for instance, when a desktop pc is running only a word-processing or when a laptop has fully charged battery and the workload for the CPU is low. Since such devices can often be run at these very light loads for a high proportion of the use, the resultant waste of energy can be considerable. The efficiency degradation will be partly due to lower efficiency of the DC/DC converter at light load; however, decreases in efficiency of the PFC circuit are usually even worse.

"Considering for the moment, Boundary Conduction Mode (BCM), it will be appreciated that to achieve at high inefficiency, the ratio of the transferred energy per cycle to the losses in that same cycle should be high. At low load, usually this is not the case, for two reasons: firstly, near to the zero crossing of the AC waveform and for low instantaneous input voltage in general, the switching frequency is very high, and yet the amount of transferred energy is low. Switching in this area of the AC voltage waveform is very inefficient--conversely, within each half cycle of the AC waveform, the instantaneous efficiency of a PFC circuit is highest when the instantaneous AC voltage is high. Secondly, at low load the peak inductor current is very low, and thus the influence of ringing time and the switching losses become increasingly dominant, since they are roughly proportional to current and frequency, and lowering of the load results in increasing the switching frequency.

"A known way to address the above problems is by the introduction of a frequency clamp. A frequency clamp prevents the switching frequency from exceeding a predetermined value. As the load is decreased, this first becomes effective around the zero crossing of the AC supply. With further decrease in load, the fraction of the half-cycle during which the clamp operates increases. Ultimately, the clamp is active during the complete half cycle. Such frequency clamps are used for instance in NXP Semiconductor's product TEA1750. Such a solution is effective for intermediate levels of load; however it does not adequately address the problem for very low loads, since the ratio of transferred power per cycle to the losses is then the still far from optimal.

"European patent application EP-A-0,580,237 relates to control of a PFC by means of adjusting the on-time on the AC half cycle by half cycle basis, but maintaining switching during the full half cycle. Switching around the zero crossing of the mains voltage is still present, and the efficiency loss due to that switching around the zero crossing is thus not resolved.

"A second known way of addressing the above problems is to use burst mode operation. In burst mode, the PFC is active only during a certain time period. The period may either be preset or derived from the output voltage. The PFC is switched off at low load, and switched on again when the output voltage of the PFC circuit has dropped to a certain minimum value. Such a method is implemented in NXP Semiconductor's TEA1750 Green-Chip III systems. Although this increases the average efficiency considerably, a major drawback remains for some applications in that the output voltage varies significantly. Although some types of DC/DC converters such as flyback can handle this relatively easily, this is not the case for all converter types. For example LLC converters are less tolerant of input voltage variations. And although it is possible to design such a converter for high input voltage variations, this has a significant influence on the efficiency during normal operation, which materially detracts from one of the major benefits of this type of converter.

"Moreover, the above known solutions are limited to the boundary conduction mode (BCM) control, and do not readily carry across to continuous conduction mode (CCM) control.

"It would be therefore be desirable to be able to operate a PFC circuit to minimise the loss in efficiency at light load whilst avoiding some of the disadvantages of the known solutions."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "It is an object of present invention to provide a method of operating a power factor correction the stage for a power supply, which is capable of operating at a high efficiency.

"A method of operating a switched mode power supply having power factor correction and supplied from an AC supply stage, the method comprising defining at least one operating window entirely within a half-cycle of the AC supply, and switching the power supply within the half-cycle only during the at least one operating window and with an on-time and a switching frequency. By disabling the switching near to zero crossing, the efficiency of the power supply can be increased without unnecessary deterioration of the power factor.

"In embodiments, there is a single window, and the operating window is such that a peak of the AC supply is included within the window. Other than in very specific circumstances, the peak of the AC supply is the time when the losses are relatively lowest, so this enables particularly high efficiencies. Alternatively, in an embodiment, the at least one operating window may comprise a first side-window and a second side-window, such that the first side-window lies to one side of a peak of the AC supply and the second side-window lies to the other side of the peak of the AC supply. This situation can be advantageous in specific circumstances where the output voltage is double the instantaneous input voltage.

"In embodiments an output characteristic of the power supply is controlled by controlling the width of the operating window, and in particular embodiments, the output characteristic is one of output power, output current and output voltage.

"In embodiments, the window is symmetrical about the peak of the AC supply. This minimises the efficiency drop which would occur from operating too close to the zero cross on either side of the peak supply. Further, very asymmetrical positioning of the window, by more than 5% or so, would lead to degradation of the power factor, which is, like the efficiency drop, disadvantageous.

"In embodiments, the on-time is constant within the operating window. Further, in some embodiments, the on-time of the power factor controller is varied between either successive half-cycles or between successive cycles. Variation of the on-time of the switching is thus possible between AC cycles--or even within an AC cycle--which may provide an alternative or additional control of the output characteristic and in particular the output power.

"In embodiments, a peak switched current is constant throughout the operating window. Further, in some embodiments, the peak switched current is varied between either successive half-cycles or between successive cycles. Similar to variation of the on-time, variation of the peak switched current is thus possible between AC cycles--or even within an AC cycle--which may provide another alternative or additional control of the output characteristic and in particular the output power. In embodiments in which one of the peak current average current, and on-time is varied within the window, the variation can beneficially be made such as to optimise the efficiency within a switching cycle. In preferred embodiments, this optimisation is for the highest efficiency per switching cycle.

"In embodiments, the switching frequency is constant throughout the operating window. In alternative embodiments, jitter is introduced into the switching frequency. In yet further alternative embodiments, an output characteristic is controlled by controlling the switching frequency. In some embodiments, the switching frequency is constrained not to exceed a predetermined clamping frequency and further control is provided by controlling the width of the operating window. Thus switching frequency can be used as a further or alternative control means, and the operation may be combined with clamping of the switching frequency.

"In embodiments a sample-and-hold function is carried out at the peak of the half-cycle of the AC supply. Alternatively or in addition, a sample-and-hold function is carried out at least one of the end and the start of the operating window. In embodiments, an output from the sample-and-hold function is used for determining the width of the operating window for a subsequent half-cycle of the AC supply. Sample-and-hold techniques provide a particularly simple and process-light means of testing for conditions under which it is appropriate to control the operating window.

"In embodiments, the switched mode power supply is supplied with an input voltage and outputs an output voltage, and in the event that the input voltage is less than half the output voltage, the on-time is controlled in dependence on the ratio between the output voltage and the input voltage.

"According to another aspect of the present invention there is provided a control circuit for a switched mode power supplied configured to operate according to a method as described above. Furthermore, in embodiments, there is provided a switched mode power supply comprising such a control.

"These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter."

For additional information on this patent, see: Pansier, Frans. PFC with High Efficiency at Low Load. U.S. Patent Number 8644041, filed January 14, 2010, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=52&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2577&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: NXP B.V., Electronics, Semiconductor.

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Source: Electronics Newsweekly


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