The patent's inventor is Rao,
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Parallel-to-serial converters are used across various computing devices and for various applications. For instance in DDR-DRAM semiconductor memories, a double data rate input to semiconductor memory is converted internally into a single data rate and written in parallel to the semiconductor memory. For a read access, the stored data in the semiconductor memory that is stored in parallel is converted into a serial data stream for output. An interface circuit of the semiconductor memory is equipped with a parallel-to-serial converter for such conversions.
"In the simplest case, a parallel-serial converter is designed as a controllable shift register. The parallel-to-serial converter has a number of cascade-connected flip-flops corresponding to the number of input terminals. Furthermore, a control signal generated by means of a multiplexer may be provided for controlling the shift register. The construction and the method of operation of such a parallel-to-serial converter designed as a controllable shift register are known in many instances.
"For a typical parallel-to-serial converter, the single multiplexer is used for parallel loading of an entire N-bit word into a shift register. The shift register then shifts the loaded data to generate serial data. After the N-bit word is shifted out, another N-bit word is retrieved for parallel loading into the shift register. The latency of such parallel-to-serial converter is very low due to its simplicity. However, the amount of power used to operate such parallel-to-serial converter is quite high. Therefore, there remains a desire for providing a parallel-to-serial converter that has low latency and low power consumption."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "An object of this invention is to provide a low power parallel-to-serial converter.
"Another object of this invention is to provide a parallel-to-serial converter that has low latency.
"Yet another object of this invention is to provide a parallel-to-serial converter that supports multiple word widths.
"Briefly, the present invention discloses methods and systems for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.
"An advantage of this invention is that a low power parallel-to-serial converter is provided.
"Another advantage of this invention is that a parallel-to-serial converter that has low latency is provided.
"Yet another advantage of this invention is that a parallel-to-serial converter that supports multiple word widths is provided."
For the URL and additional information on this patent, see: Rao,
Keywords for this news article include: Electronics, Semiconductor,
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