News Column

Patent Issued for Package-On-Package Technology for Fan-Out Wafer-Level Packaging

February 18, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Kaufmann, Matthew Vernon (Morgan Hill, CA); Tan, Teck Yang (Singapore, SG), filed on July 30, 2009, was published online on February 4, 2014.

The assignee for this patent, patent number 8643164, is Broadcom Corporation (Irvine, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to integrated circuit packaging technology, and more particularly to package-on-package technology.

"Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB.

"An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are interfaced with the IC chip when the IC chip has not yet been singulated from its fabrication wafer. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.

"A current move to tighter fabrication process technologies, such as 65 nm, with a continuing need to meet strict customer reliability requirements and ongoing cost pressures, is causing difficulties in implementing wafer-level BGA package technology. For example, due to the small size of the die used in wafer-level BGA packages, in some cases there is not enough space to accommodate all of the package pins at the pin pitch required for the end-use application. Furthermore, it is desired to include additional functionality in wafer-level BGA packages. Including additional functionality in wafer-level BGA packages is difficult due to their small size.

"Multiple integrated circuit packages may be stacked upon one another to provide additional functionality in a package-on-package (POP) structure. However, POP assembly techniques are difficult to implement in small integrated circuit packages. For example, current POP assembly techniques are not applicable to wafer-level integrated circuit packages."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. In particular, techniques for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

"In a first implementation, a method for forming integrated circuit (IC) package structures is provided. A first plurality of electrically conductive features is formed on a first surface of a substrate. A first plurality of electrically conductive paths is formed through the substrate that is electrically coupled to the first electrically conductive features on the first surface of the substrate. A non-active surface of each of a plurality of integrated circuit dies is attached to the first surface of the substrate. Each integrated circuit die includes an integrated circuit region having a plurality of terminals. A substantially planar layer of an insulating material is formed over the first surface of the substrate to cover the dies on the substrate. A second plurality of electrically conductive paths is formed through the insulating material. A second plurality of electrically conductive features is formed on a second surface of the substrate. At least one redistribution interconnect is formed on the insulating material for each die of the plurality of dies. Each redistribution interconnect has a first portion coupled to a terminal of a respective die and a second portion that extends away from the first portion over a portion of the insulating material adjacent to the respective die. The second portion is coupled to an electrically conductive path of the second plurality of electrically conductive paths. A ball interconnect is coupled to each second portion. The dies are singulated into a plurality of first integrated circuit packages that each includes a die of the plurality of dies and the portion of the insulating material adjacent to the included die. A respective second integrated circuit package is mounted to each of the plurality of first integrated circuit packages to form a plurality of package-on-package structures.

"In a further aspect, a substantially planar layer of a thick film material may be formed on the first surface of the substrate. A plurality of openings may be formed in the layer of the thick film material. During the attaching of the dies to the substrate, a non-active surface of each of the plurality of dies may be attached to a first surface of a substrate in a corresponding opening of the plurality of openings. In such an implementation, the substantially planar layer of insulating material is formed on the layer of the thick film material to cover the dies in the openings on the substrate. The dies may be singulated into the plurality of integrated circuit packages that each includes a die of the plurality of dies, the portion of the insulating material adjacent to the included die, and a portion of the thick film material adjacent to the included die.

"In a still further aspect, a method of forming the redistribution interconnects on the insulating material is provided. A plurality of first vias is formed through the substantially planar layer of the insulating material to provide access to the plurality of terminals. A plurality of redistribution interconnects is formed on the substantially planar layer of the insulating material. The first portion of each redistribution interconnect is in contact with a respective terminal though a respective first via. A second layer of insulating material is formed over the substantially planar layer of insulating material and the plurality of redistribution interconnects. The plurality of second vias is formed through the second layer of insulating material to provide access to the second portion of each of the plurality of redistribution interconnects. A plurality of under bump metallization layers is formed on the second layer of insulating material such that each under bump metallization layer is in contact with the second portion of a respective redistribution interconnect though a respective second via.

"In a still further aspect, the second integrated circuit packages may be mounted to each of the plurality of first integrated circuit packages by coupling electrical mounting members of each second integrated circuit package to the second plurality of electrically conductive features of a corresponding first integrated circuit package to form the plurality of package-on-package structures.

"In another implementation, an integrated circuit (IC) package structure is provided. The package structure includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes an integrated circuit die, a substrate, a first layer of an insulating material, first and second electrically conductive paths, a redistribution interconnect, and a ball interconnect. The integrated circuit die has a plurality of terminals on a first surface of the integrated circuit die. The substrate has opposing first and second surfaces. The first surface of the substrate has a first electrically conductive feature. The second surface of the substrate has a second electrically conductive feature. The first electrically conductive path is through the substrate from the first electrically conductive feature to the second electrically conductive feature. The second surface of the integrated circuit die is attached to the first surface of the substrate. The first layer of insulating material covers the first surface of the die and the first electrically conductive feature, and fills a space adjacent to at least one side of the die on first surface of the substrate. The second electrically conductive path is through the insulating material, and is coupled to the first electrically conductive feature. The redistribution interconnect is on the first layer of the insulating material, and includes a first portion and a second portion. The first portion is coupled to a terminal of the die through the first layer. The second portion extends away from the first portion over the insulating material that fills the space adjacent to the die. The second portion is coupled to the second electrically conductive path. The ball interconnect is coupled to the second portion of the redistribution interconnect. The second integrated circuit package is mounted to the first integrated circuit package.

"In a further aspect, the first integrated circuit package may include a substantially planar thick film material that is attached to the first surface of the substrate. The thick film material forms an opening. The integrated circuit die is positioned in the opening on the first surface of the substrate. The first layer of insulating material covers the first surface of the die, the first electrically conductive feature, and a surface of the thick film material, and fills a space adjacent to the die in the opening.

"In another implementation, a wafer level integrated circuit package structure is provided. The wafer level integrated circuit package structure includes a substrate, a plurality of integrated circuit dies, an insulating material, a first plurality of electrically conductive paths, a second plurality of electrically conductive paths, and a plurality of redistribution interconnects. The substrate has opposing first and second surfaces. The substrate including a first plurality of electrically conductive features on a first surface of a substrate that are coupled by the first plurality of electrically conductive paths through the substrate to a second plurality of electrically conductive features on the second surface of the substrate. The integrated circuit dies each include an integrated circuit region. A non-active surface of each die of the plurality of dies is attached to a first surface of the substrate. An insulating material covers the dies on the substrate. The second plurality of electrically conductive paths is formed through the insulating material. The plurality of redistribution interconnects is on the insulating material. The plurality of redistribution interconnects includes a redistribution interconnect for each die of the plurality of dies having a first portion coupled to a terminal of a respective die and a second portion that extends away from the first portion over a portion of the insulating material adjacent to the respective die. The second portion is coupled to an electrically conductive path of the second plurality of electrically conductive paths.

"These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention. Note that the Summary and Abstract sections may set forth one or more, but not all exemplary embodiments of the present invention as contemplated by the inventor(s)."

For more information, see this patent: Kaufmann, Matthew Vernon; Tan, Teck Yang. Package-On-Package Technology for Fan-Out Wafer-Level Packaging. U.S. Patent Number 8643164, filed July 30, 2009, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=69&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3445&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: Technology, Broadcom Corporation.

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Source: Journal of Technology


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