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Patent Issued for Method of Generating a Layout of an Integrated Circuit Comprising Both Standard Cells and at Least One Memory Instance

February 20, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- A patent by the inventors Yeung, Gus (Austin, TX); Kinkade, Martin Jay (Austin, TX); Frederick, Jr., Marlin Wayne (Austin, TX), filed on October 23, 2012, was published online on February 4, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8645893 is assigned to ARM Limited (Cambridge, GB).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a technique for generating a layout of an integrated circuit, where the layout incorporates both standard cells defining functional components of the integrated circuit and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit.

"It is becoming more and more common for integrated circuits to include on-chip memory devices, a particular example being where the integrated circuit provides a System-on-Chip (SoC).

"When designing memory devices, there are two general approaches that can be taken. In accordance with a first approach, the memory device can be custom designed for a particular implementation, which may lead to an efficient design. However, the disadvantage of such an approach is that there is little chance of re-using that design in different implementations, and accordingly such an approach is costly. In accordance with an alternative approach, a memory architecture is developed specifying a definition of circuit elements and data defining rules for combining those circuit elements, and then a memory compiler tool is used to create a memory instance (i.e. a particular instantiation) of that memory architecture to form the design of a required memory device having regard to some specified properties of that memory device. This latter approach of using a memory compiler tool to generate a memory instance is nowadays a very popular technique, since once the memory architecture is defined, a wide variety of different instances of a memory device can be readily generated, having regards to the requirements of the memory device in any particular system.

"Accordingly, when designing SoCs including one or more on-chip memory devices, it is typically the case that the required memory instance(s) will be generated by a memory compiler, with each generated memory instance then being provided to a place and route tool used to generate the layout of the integrated circuit.

"The place and route tool is an automated tool which uses a functional design of a planned integrated circuit (for example in the form of a gate level net list, or a Register Transfer Level (RTL) higher level representation of the design such as may be provided by a Verilog model) and a cell library providing a set of standard cells (the standard cells defining functional components, and being 'building blocks' for putting together the layout of the integrated circuit according to the functional design) in order to generate the layout of an integrated circuit. If the integrated circuit is also to include one or more memory devices, then the place and route tool needs to place the memory instance representing each such memory device within the layout and then place the required standard cells around the memory instance(s) in order to form the layout of the integrated circuit according to the specified functional design.

"However, such an approach can lead to inefficiencies in the usage of space resulting in the layout including one or more areas that do not contribute useful functionality. This may for example be due to there being wasted space at a boundary of a memory instance that is of insufficient size to accommodate standard cells, or due to the need to provide separation structures at the interface between the memory and the standard cells, such as may be required in the polysilicon layer of the integrated circuit layout.

"This inefficient space usage contributes to the overall area required for the integrated circuit, and generally the larger the area of the integrated circuit, the larger the cost involved in the manufacture of the integrated circuit.

"The cost implications of this inefficient space usage become more significant as more memory instances are included in integrated circuits, as the individual memory instances are made smaller (where the wasted space becomes a larger proportion of the overall area associated with the memory instance) and/or as process geometries shrink in modern data processing systems (since typically the separation structures required between the memory instance and the standard cells in the polysilicon layer become relatively larger as the process geometries shrink).

"Accordingly, it would be desirable to provide an improved technique for generating the layout of an integrated circuit in situations where the layout will incorporate both standard cells and at least one memory instance generated by a memory compiler."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Viewed from a first aspect, the present invention provides a method of generating a layout of an integrated circuit, the layout incorporating standard cells defining functional components of the integrated circuit and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit, the method comprising: providing the memory compiler with a memory architecture specifying a definition of circuit elements and data defining rules for combining those circuit elements in order to generate memory instances conforming to the memory architecture; receiving input data specifying one or more properties of a desired memory instance; employing the memory compiler to generate the desired memory instance based on said input data such that the desired memory instance conforms to said memory architecture; providing a standard cell library, each standard cell within the standard cell library defining a corresponding functional component; in an integration enhancement mode of operation of the memory compiler, causing the memory compiler to reference at least one property of the standard cell library in order to generate the desired memory instance in a form that will reduce an area overhead associated with a boundary between that desired memory instance and surrounding standard cells when that desired memory instance is integrated into the layout; and generating the layout by populating standard cell rows extending in a first direction with standard cells selected from said standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

"In accordance with the present invention, the memory compiler is provided with an integration enhancement mode of operation where the memory compiler references at least one property of the standard cell library prior to generating the desired memory instance. By taking that at least one property of the standard cell library into account, the memory compiler is then able to generate the desired memory instance in a form that will reduce an area overhead associated with a boundary between that desired memory instance and the surrounding standard cells when that desired memory instance is integrated into the layout.

"There are a number of properties of the standard cell library that can be referred to by the memory compiler. For example, in one embodiment, the design of the standard cells of the standard cell library may be such that they do not allow free space between the standard cells and an edge of the memory instance but instead require the standard cells to abut directly against an edge of the memory instance. In that scenario, the memory compiler can take that property into account in order to generate the desired memory instance in a form that will reduce the width of a polysilicon interface region required within the polysilicon layer to separate the desired memory instance from adjacent standard cells. Considering another example, the at least one property of the standard cell library referenced by the memory compiler may be the height specified for the standard cell rows, and by taking that property into account the memory compiler can be arranged to generate a desired memory instance in a form such that the width of the desired memory instance is constrained to be a integer multiple of the row height, thereby removing any wasted space that might otherwise be present.

"Whilst the above-mentioned property of the standard cell library may be provided as an input to the memory compiler during operation of the compiler, in an alternative embodiment this property may be understood and designed into the memory compiler and standard cell library, hence avoiding the need for any such input to the memory compiler during operation.

"The integration enhancement mode of operation may be the only mode of operation of the memory compiler, or may be one of a number of modes of operation available to the memory compiler.

"In one embodiment, the method further comprises providing the memory compiler with at least one further mode of operation in which the memory compiler does not reference said at least one property of the standard cell library when generating the desired memory instance, resulting in an increase in said area overhead associated with said boundary when that desired memory instance is integrated into the layout, when compared with the area overhead associated with said boundary when the memory compiler is operated in said integration enhancement mode of operation. By provision of the at least one further mode of operation, backwards compatibility can be ensured, thereby allowing the memory compiler to be used, for example, in situations where the properties of the standard cell library are such that they do not allow the memory compiler to employ the integration enhancement mode of operation.

"In one embodiment, the layout includes a polysilicon layer comprising a plurality of polysilicon tracks extending in a second direction through the polysilicon layer, the second direction being orthogonal to said first direction that the standard cell rows extend in. The polysilicon layer includes at least one polysilicon interface region separating the desired memory instance from adjacent standard cells, each said at least one polysilicon interface region providing a separation distance extending in said first direction. Said at least one property of the standard cell library referenced by the memory compiler in said integration enhancement mode of operation may be a property indicating that the design of the standard cells of that standard cell library require the standard cells to abut directly against an edge of the desired memory instance extending in said second direction. If so, in said integration enhancement mode of operation of the memory compiler, the memory compiler generates the desired memory instance in a form that will reduce the separation distance of the polysilicon interface region when that desired memory instance is integrated into the layout.

"The polysilicon interface region can take a variety of forms. However, in one embodiment each said at least one polysilicon interface region comprises dummy polysilicon tracks extending in said second direction, and in said integration enhancement mode of operation of the memory compiler, the memory compiler generates the desired memory instance in a form that will reduce the number of dummy polysilicon tracks in the polysilicon interface region. Accordingly, in such an embodiment, since it is known that the standard cell library has constrained the design of the standard cells such that the standard cells are required to abut directly against an edge of the desired memory instance extending in the second direction, the number of dummy polysilicon tracks that the memory compiler needs to generate in association with the desired memory instance can be reduced, giving an overall reduction in the separate distance of the polysilicon interface region.

"In one particular embodiment, each said at least one polysilicon interface region comprises a first interface sub-region associated with the desired memory instance and a second interface sub-region associated with standard cells. The property indicating that the design of the standard cells of that standard cell library require the standard cells to abut directly against an edge of the desired memory instance extending in said second direction is a property identifying a reduction in the number of dummy polysilicon tracks provided in the second interface sub-region. In the integration enhancement mode of operation of the memory compiler, the memory compiler generates the desired memory instance in a form having less dummy polysilicon tracks in the first interface sub-region than would be provided if the memory compiler were operated in at least one further mode of operation in which the memory compiler did not reference said at least one property of the standard cell library when generating the desired memory instance. Hence, in such an arrangement, by placing a constraint on the standard cell design, and then taking that constraint into account when using the memory compiler to generate memory instances, a reduction in the number of dummy polysilicon tracks in both the first interface sub-region and the second interface sub-region can be achieved, thereby giving significant area savings in the layout of the integrated circuit.

"The dummy polysilicon tracks can take a variety of forms. In one embodiment, in said at least one further mode of operation the first interface sub-region would include as said dummy polysilicon tracks at least one supporting dummy track and at least one terminating dummy track having a thickness in said first direction greater than the thickness of each supporting dummy track. However, in said integration enhancement mode of operation of the memory compiler, the memory compiler generates the desired memory instance in a form where the first interface sub-region includes no terminating dummy track. The ability to remove the terminating dummy track gives rise to some significant space savings. In one particular embodiment, the second interface sub-region also includes no terminating dummy track, thus further improving the space savings.

"In many layouts, the pitch spacing of the polysilicon tracks (also referred to as the 'poly pitch') within the portion of the polysilicon layer associated with the desired memory instance is different to the poly pitch of the polysilicon tracks within sections of the polysilicon layer associated with standard cells. However, in one embodiment, the poly pitch in both sections is arranged to be the same, and in that embodiment when the memory compiler is operating in the integration enhancement mode of operation, it is able to generate a desired memory instance in a form that will additionally reduce the number of supporting dummy tracks in each polysilicon interface region. In one particular embodiment, such an approach may result in only a single supporting dummy track being required within each polysilicon interface region.

"In embodiments where the memory instance is placed partway along the length of the standard cell rows, thereby splitting a number of standard cell rows into two portions, a first polysilicon interface region will be formed at a first side of the desired memory instance and a second polysilicon interface region will be formed at an opposing side of the desired memory instance, both the first side and the opposing side extending in the second direction. Accordingly, in such embodiments, the above mentioned space savings can be realised in association with both polysilicon interface regions.

"In one particular embodiment, due to the way in which the polysilicon tracks run within the design of a memory instance compared with the direction in which they run within standard cell rows, the memory instance is turned through 90 degrees prior to placement within the layout, such that the first side of the desired memory instance forms the top of the memory instance and the opposing side forms the bottom of the memory instance. The rows of memory cells within the memory instance then run along the second direction, i.e. tangential to the standard cell rows, and in parallel with the polysilicon tracks.

"In addition to, or as an alternative to, the memory compiler considering the earlier-mentioned property of the standard cell library, the memory compiler may take into account the row height specified by the standard cell library. In particular, in one embodiment, the standard cell rows have a row height extending in a second direction orthogonal to said first direction, the row height being defined by the standard cell library. The at least one property of the standard cell library referenced by the memory compiler in said integration enhancement mode of operation may be said row height, and then in said integration enhancement mode of operation of the memory compiler, the memory compiler generates the desired memory instance in a form where the width of the desired memory instance in said second direction is constrained to be an integer multiple of the row height.

"There are a number of ways in which the memory compiler can constrain the desired memory instance such that its width in the second direction is an integer multiple of the row height. In one embodiment, the memory instance comprises at least one memory array and a plurality of logic circuits coupled to each memory array, and in the integration enhancement mode of operation the memory compiler constrains the width of each memory array in the second direction to be an integer multiple of the row height.

"In one particular embodiment, the width of each memory array in the second direction is dictated by the number of memory cells provided within each row of the memory array, and in the integration enhancement mode of operation, the memory compiler constrains the number of memory cells provided within each row of each memory array such that the width of each memory array in said second direction is said integer multiple of the row height.

"There are a number of ways of constraining the number of memory cells provided within each row. For example, in one embodiment the possible word sizes of data to be stored within the memory array can be constrained so that the overall number of memory cells provided within each row ensures that the width of the memory array in the second direction is an integer multiple of the row height. In particular, each row will be constrained to store a predetermined number of words, where each word comprises a plurality of bits, and where each bit is stored in a memory cell. By appropriate constraint of the word size, this will constrain the number of memory cells in each row such that that number can only increase in units which ensure that the width of the memory array is equal to an integer multiple of the row height. Similarly, the multiplexing options of the memory array can be constrained to ensure that the number of memory cells in each row can only grow in units which are constrained to be an integer multiple of a row height. For example, if the memory design has a MUX-4 configuration, then the length of each row can only increase by four memory cells at a time, if the memory device has a MUX-8 configuration, then the length of each row can only increase by eight memory cells at a time, etc. By constraining the muxing configurations and/or the possible word sizes, it is possible then to ensure that the rows can only increase in increments which conform to multiples of the row height.

"Alternatively or in addition, the memory compiler may constrain the width of the plurality of logic circuits coupled to each memory array so that those logic circuits have a width in the second direction which is constrained to be an integer multiple of the row height.

"In addition to the memory arrays and associated logic circuits coupled to those memory arrays, it is known for memory instances to include edge cells. In one embodiment, in the integration enhancement mode of operation, the memory compiler selects a width of the edge cells in said second direction such that the width of the desired memory instance in said second direction is constrained to be an integer multiple of the row height. This constraint on the edge cell width can be used instead of, or in addition to, the earlier-described measures for constraining the width of the memory instance to be an integer multiple of the row height.

"Viewed from a second aspect, the present invention provides a storage medium storing a memory compiler computer program for controlling a computer to generate a desired memory instance from a memory architecture associated with the memory compiler computer program, the memory architecture specifying a definition of circuit elements and data defining rules for combining those circuit elements, the memory compiler computer program having an integration enhancement mode of operation in which, during performance of a method of generating a layout of an integrated circuit, where the layout incorporates standard cells defining functional components of the integrated circuit and at least one memory instance defining a memory device of the integrated circuit, the memory compiler computer program is configured to reference at least one property of a standard cell library defining said standard cells in order to generate the desired memory instance in a form that will reduce an area overhead associated with a boundary between that desired memory instance and surrounding standard cells when that desired memory instance is integrated into the layout. In one embodiment, the storage medium can take the form of a non-transitory storage medium."

URL and more information on this patent, see: Yeung, Gus; Kinkade, Martin Jay; Frederick, Jr., Marlin Wayne. Method of Generating a Layout of an Integrated Circuit Comprising Both Standard Cells and at Least One Memory Instance. U.S. Patent Number 8645893, filed October 23, 2012, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=15&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=743&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: ARM Limited.

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