News Column

Patent Issued for Fault Support in an Emulation Environment

February 20, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Durand, Eric (La Ville du Bois, FR); Reymond, Estelle (Orsay, FR); Fadel, John (Les Ulis, FR), filed on June 24, 2013, was published online on February 4, 2014.

The assignee for this patent, patent number 8645118, is Mentor Graphics Corporation (Wilsonville, OR).

Reporters obtained the following quote from the background information supplied by the inventors: "Today's sophisticated SoC (System on Chip) designs are rapidly evolving and nearly doubling in size with each generation. Indeed, complex designs have nearly exceeded 50 million gates. This complexity, combined with the use of devices in industrial and mission-critical products, has made complete design verification an essential element in the semiconductor development cycle. Ultimately, this means that every chip designer, system integrator, and application software developer must focus on design verification.

"Hardware emulation provides an effective way to increase verification productivity, speed up time-to-market, and deliver greater confidence in the final SoC product. Even though individual intellectual property blocks may be exhaustively verified, previously undetected problems can appear when the blocks are integrated within the system. Comprehensive system-level verification, as provided by hardware emulation, can test overall system functionality, IP subsystem integrity, specification errors, block-to-block interfaces, boundary cases, and asynchronous clock domain crossings. Although design reuse, intellectual property, and high-performance tools all help by shortening SoC design time, they do not diminish the system verification bottleneck, which can consume 60-70% of the design cycle. As a result, designers can implement a number of system verification strategies in a complementary methodology including software simulation, simulation acceleration, hardware emulation, and rapid prototyping. But, for system-level verification, hardware emulation remains a favorable choice due to superior performance, visibility, flexibility, and accuracy.

"A short history of hardware emulation is useful for understanding the emulation environment. Initially, software programs would read a circuit design file and simulate the electrical performance of the circuit very slowly. To speed up the process, special computers were designed to run simulations as fast as possible. IBM'sYorktown 'simulator' was the earliest (1982) successful example of this as it used multiple processors running in parallel to run the simulation. Each processor was programmed to mimic a logical operation of the circuit for each cycle and could be reprogrammed in subsequent cycles to mimic a different logical operation. This hardware `simulator` was faster than the current software simulators, but far slower than the end-product ICs. When Field Programmable Gate Arrays (FPGAs) became available in the mid-80's, circuit designers conceived of networking hundreds of FPGAs together in order to map their circuit design onto the FPGAs and the entire FPGA network would mimic, or emulate, the entire circuit. In the early 90's the term 'emulation' was used to distinguish reprogrammable hardware that took the form of the design under test (DUT) versus a general purpose computer (or work station) running a software simulation program.

"Soon, variations appeared. Custom FPGAs were designed for hardware emulation that included on-chip memory (for DUT memory as well as for debugging), special routing for outputting internal signals, and for efficient networking between logic elements. Another variation used custom IC chips with networked single bit processors (so-called processor based emulation) that processed in parallel and usually assumed a different logic function every cycle.

"Physically, a hardware emulator resembles a large server. Racks of large printed circuit boards are connected by backplanes in ways that most facilitate a particular network configuration. A workstation connects to the hardware emulator for control, input, and output. Before the emulator can emulate a DUT, the DUT design must be compiled. That is, the DUT's logic must be converted (synthesized) into code that can program the hardware emulator's logic elements (whether they be processors or FPGAs). Also, the DUT's interconnections must be synthesized into a suitable network that can be programmed into the hardware emulator. The compilation is highly emulator specific and can be time consuming. After the compilation is complete, the design is downloaded into the emulator.

"Some integrated circuits in the emulator can be faulty or become faulty over time (i.e., malfunctioning or defective), which can lead to an unacceptable emulation of a downloaded design. Correction through re-compilation is time consuming and wasteful."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "An emulator is disclosed that allows for diagnoses of failures or defects within the emulator. A map of faulty resources can be generated to identify which resources should be avoided during compilation. Thus, desirably in a transparent and automated manner, emulator defects found during diagnostics can be stored in a database or in formatted output files. A compiler has access to the database or formatted output files and can compile the design taking into account (e.g., avoiding the use of) defective or unusable resources.

"In another embodiment, the defects of an emulator board can be stored on the emulator board itself. This allows each board to store its own maintenance information that can be used, for example, at the manufacturing site for changing defective chips. Defects stored on the board itself allow the defects to be obtained independent of the position of a board within the emulator to simplify identification of the faulty resource.

"In another embodiment, the emulator can check the current state of faulty resources on an emulator board and compare the faults to a compiled design to be downloaded. If the compiled design uses faulty resources an error condition can be indicated.

"In another embodiment, a unique database is created when powering on the emulator, built from fault information received from the emulator boards. When new faults are detected during diagnostics or input by a user, such faults are sent to the appropriate emulator boards containing those faults for being stored onboard in non-volatile memory.

"The foregoing features and advantages of embodiments will become more apparent from the following detailed description, which proceeds with reference to the accompanying figures."

For more information, see this patent: Durand, Eric; Reymond, Estelle; Fadel, John. Fault Support in an Emulation Environment. U.S. Patent Number 8645118, filed June 24, 2013, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=31&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1509&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: Software, Mentor Graphics Corporation.

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Source: Computer Weekly News


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