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Patent Issued for Apparatus and Method for Determining a Read Level of a Flash Memory after an Inactive Period of Time

February 18, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventors Cometti, Aldo G. (San Diego, CA); Huang, Lun Bin (San Diego, CA); Melik-Martirosian, Ashot (San Diego, CA), filed on July 8, 2011, was published online on February 4, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8644099 is assigned to STEC, Inc. (Santa Ana, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Flash memory bears little resemblance to a magnetic recording system. Commodity flash chips are closed systems with no external access to analog signals, in sharp contrast to the typical Hard Disk Drive (HDD) where analog signals have always been available for study. Even though the HDD is a complex electro-mechanical system and can suffer catastrophic failure, it has been possible to engineer drives to have a life expectancy with little to no degradation in performance, which extend beyond their time of technical obsolescence. The performance of flash memory, on the other hand, is known to degrade through the life cycle and has a finite life. Consequently, since flash memory was first conceived as a memory device the target error rate at the output of the chip has been very low, as opposed to systems where stronger Error Correction Coding (ECC) may be used.

"Lower priced Solid State Drives (SSD) are typically manufactured using multi-level cell (MLC) flash memory for increased data capacity, but MLC is less reliable than single-level cell (SLC) flash memory. Consumer SSD manufacturers have mitigated such problems by employing interleaving and/or providing excess capacity in conjunction with wear-leveling algorithms. MLC flash endurance, however, has not been proven acceptable for enterprise SSD applications. Even with the increased data capacity of MLC, it becomes more expensive in enterprise applications because of its disproportionately large decrease in program/erase (P/E) cycles over time due to increased (wear causing) stresses required to read, program and erase the flash, causing a gradual degradation in endurance."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A method for determining a dwell time in a memory circuit after a shutdown of the memory circuit is disclosed. In one aspect, the method includes storing a first test block before the shutdown, storing a second test block after powering on the memory circuit, performing a first read level sweep of the first test block to determine a first read level voltage with minimum errors, including determining (for example, calculating) the first read level voltage as a function of a nominal read level voltage and a first estimation parameter, performing a second read level sweep of the second test block to determine a second read level voltage with minimum errors, including determining the second read level voltage as a function of the nominal read level voltage and a second estimation parameter, determining a shutdown V.sub.T shift as a function of the first read level voltage and the second read level voltage, and determining a shutdown duration as a function of the shutdown V.sub.T shift.

"Also disclosed is a control circuit for determining a dwell time in a memory circuit after a shutdown of the memory circuit. In one aspect, the control circuit includes a memory interface configured to be operably coupled to the memory circuit, and a controller. The controller of the control circuit may be configured to store a first test block before the shutdown, save a second test block after the memory circuit is powered on, perform a first read level sweep of the first test block to determine a first read level voltage with minimum errors, including determining the first read level voltage as a function of a nominal read level voltage and a first estimation parameter, perform a second read level sweep of the second test block to determine a second read level voltage with minimum errors, including determining the second read level voltage as a function of the nominal read level voltage and a second estimation parameter, calculate a shutdown V.sub.T shift as a function of the first read level voltage and the second read level voltage, and calculate a shutdown duration as a function of the shutdown V.sub.T shift.

"Also disclosed is a system for determining a dwell time in a memory circuit after a shutdown of the memory circuit. In one aspect, the system includes a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device, a temperature sensor, a storage medium interface operably coupled to a volatile memory, a memory interface operably coupled to the memory circuit, and a controller. The controller of the system may be operable to store a first test block before the shutdown, save a second test block after the memory circuit is powered on, perform a first read level sweep of the first test block to determine a first read level voltage with minimum errors, including determining the first read level voltage as a function of a nominal read level voltage and a first estimation parameter, perform a second read level sweep of the second test block to determine a second read level voltage with minimum errors, including determining the second read level voltage as a function of the nominal read level voltage and a second estimation parameter, calculate a shutdown V.sub.T shift as a function of the first read level voltage and the second read level voltage, and calculate a shutdown duration as a function of the shutdown V.sub.T shift.

"In some aspects, the method, control circuit, and/or system may include the controller storing a pre-shutdown temperature before the shutdown and determining the dwell time as a function of the current time and the block time stamp and the revised duration may include retrieving a pre-shutdown temperature and the block time stamp, determining a temperature acceleration factor as a function of the drive temperature and the pre-shutdown temperature, and determining the dwell time as a function of the current time, the block time stamp, the revised duration, and the temperature acceleration factor. In other aspects, the method, control circuit, and/or system may include determining a temperature acceleration factor as a function of a drive temperature, determining a current aging time as a function of a current time value and the temperature acceleration factor, determining an post-shutdown aging time as a function of the current aging time and the shutdown duration, reading a block time stamp, and determining the dwell time by subtracting the block time stamp from the post-shutdown aging time.

"It is understood that other configurations of the subject technology will become readily apparent to those skilled in the art from the following detailed description, wherein various configurations of the subject technology are shown and described by way of illustration. As will be realized, the subject technology is capable of other and different configurations and its several details are capable of modification in various other respects, all without departing from the scope of the subject technology. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive."

URL and more information on this patent, see: Cometti, Aldo G.; Huang, Lun Bin; Melik-Martirosian, Ashot. Apparatus and Method for Determining a Read Level of a Flash Memory after an Inactive Period of Time. U.S. Patent Number 8644099, filed July 8, 2011, and published online on February 4, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=51&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2519&f=G&l=50&co1=AND&d=PTXT&s1=20140204.PD.&OS=ISD/20140204&RS=ISD/20140204

Keywords for this news article include: STEC Inc., Technology.

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Source: Journal of Technology


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