No assignee for this patent application has been made.
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a package structure, particularly to a semiconductor package structure capable of reducing warpage and preventing delamination.
"As known in the art, semiconductor integrated circuits are fabricated on a semiconductor wafer by using a number of process steps, for example, film deposition, ion implantation, etching and lithographic processes. After wafer fabrication, the wafer is subjected to die singulation process that is typically performed by using a saw blade. The individual die is then packaged together with a package substrate or chip carrier. Typically, during a packaging process, the chip or die is encapsulated by molded polymer resin that also partially encapsulating a top surface of the package substrate on which the die is mounted.
"One problem with the molded plastic package is that subsequent to molding, internal delamination frequently occurs. In severe cases, a crack develops, creating an ingress site for contaminants resulting in reliability issue of the chip package. The location that is particularly prone to delamination is the interface of the package substrate and the molding resin. Delamination at the interface of the package substrate and the molding resin is primarily due to inadequate adhesion between the substrate and the molding resin and/or stresses generated by coefficient of thermal expansion mismatch and singularizing process. Another problem with the molded plastic package is the package warpage induced by thermal stress and package structure unbalance."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "It is one object of the invention to provide an improved semiconductor package structure to overcome the above-mentioned prior art problems and shortcomings.
"According to one aspect of the present invention, a semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface; a semiconductor device mounted on the first surface; a plurality of bond wires electrically coupling the semiconductor device to the package substrate; and a mold cap encapsulating at least the semiconductor device and the bond wires, wherein the mold cap comprises a vertical extension portion covering the entire sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface.
"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a schematic, cross-sectional diagram showing a semiconductor package structure capable of reducing warpage and preventing delamination in accordance with one embodiment of this invention.
"FIG. 2 is a schematic, cross-sectional diagram showing a semiconductor package structure capable of reducing warpage and preventing delamination in accordance with another embodiment of this invention."
For additional information on this patent application, see: Lin, Po-Chun. Semiconductor Package Structure. Filed
Keywords for this news article include: Patents, Electronics, Semiconductor.
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