No assignee for this patent application has been made.
News editors obtained the following quote from the background information supplied by the inventors: "High voltage integrated circuits (HVICs) in which one or more high voltage transistors are disposed with low voltage circuits on a single chip are being widely applied to power control systems such as switching power supplies and motor drivers. A high voltage integrated circuit (HVIC) includes a high voltage unit, a low voltage unit, and a junction termination disposed between the high voltage unit and the low voltage unit. The junction termination is a region that electrically separates the high voltage unit from the low voltage unit. Level shift devices that level down-shift a signal received from the high voltage unit and provide the signal to the low voltage unit are disposed in the junction termination.
"Level shift devices include lateral diffusion MOS (LDMOS) transistors. LDMOS transistors are required to maintain a high breakdown voltage and minimize an on-resistance. By using a reduced surface field (RESURF) technique, a high breakdown voltage may be obtained while an LDMOS transistor has a low on-resistance."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.
"The concepts described herein can relate to a power semiconductor device, and more particularly, to a high voltage power semiconductor device in which lateral diffusion metal oxide semiconductor (LDMOS) transistors for a level shift are electrically isolated from a high voltage unit. The concepts provide a power semiconductor device including level shift devices with enhanced reliability in which, for example, generation of cross talk can be prevented.
BRIEF DESCRIPTION OF THE DRAWINGS
"Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
"FIGS. 1A and 1B are plan views of power semiconductor devices according to embodiments, respectively;
"FIG. 2 is a cross-sectional view of a power semiconductor device according to an embodiment, for example, taken along a line II-II' of FIG. 1A;
"FIGS. 3A to 3G are cross-sectional views for describing a method of manufacturing the power semiconductor device of FIG. 2;
"FIG. 4 is a graph illustrating results of a simulation for describing current characteristics of a power semiconductor device according to an embodiment; and
"FIG. 5 illustrates results of a simulation for describing breakdown voltage characteristics of a power semiconductor device according to an embodiment."
For additional information on this patent application, see: KIM, Min-suk; LEE, Sun-hak; MOON, Jin-woo; KIM, Hye-mi. Power Semiconductor Device. Filed
Keywords for this news article include: Patents, Electronics, High Voltage, Semiconductor.
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