The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The disclosed subject matter relates generally to semiconductor devices and, more particularly, to a memory cell with asymmetric read port transistors.
"Semiconductor memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. There are many types of memory devices, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), ROMs (Read Only Memory), etc., each of which has its own advantages and disadvantages relative to other types of memory devices. For example, SRAMs are typically employed in applications where higher speed and/or reduced power consumption is important, e.g., cache memory of a microprocessor, mobile phones and other mobile consumer products, etc. Millions of such memory devices are typically included in even very basic electronic consumer products.
"Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge (HIGH) is stored in the memory device to represent a digital '1', while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital '0'. Special read/write circuitry is used to access the memory device to store digital information on such a memory device and to determine whether or not a charge is presently stored in the memory device. These program/erase cycles ('P/E cycles') typically occur millions of times for a single memory device over its effective lifetime.
"In general, efforts have been made to reduce the physical size of such memory devices, particularly reducing the physical size of components of the memory devices, such as transistors, to increase the density of memory devices, thereby increasing performance and decreasing the costs of the integrated circuits incorporating such memory devices. Increases in the density of the memory devices may be accomplished by forming smaller structures within the memory device and by reducing the separation between the memory devices and/or between the structures that make up the memory device. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced sizes of the memory device or its components, or such modifications are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many modern-day conventional integrated circuits are made possible by improvements in design, such as reduced gate insulation thicknesses in the component transistors and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
"Making SRAMs in accordance with smaller design rules, as well as using reduced internal operating voltages, can reduce the stability of
"In SRAM cells, the read margin is a performance parameter that limits the size of the achievable cells. The pass transistor must allow the memory cell to be read without reducing the charge at the storage node far enough to turn off the pull-down transistor. The sizes and/or doping characteristics of the pass and pull-down transistors are controlled to provide an adequate read margin. To reduce the constraints associated with maintaining the read margin, a conventional
"This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
"One aspect of the disclosed subject matter is seen in a memory cell including a storage element and a read port. The read port includes a first transistor having a first gate coupled to the storage element, a first source region, and a first drain region. The second transistor includes a second gate, a second source region coupled to the first drain region, and a second drain region. A first dopant profile of the first and second source regions is asymmetric with respect to a second dopant profile of the first and second drain regions.
"Another aspect of the disclosed subject matter is seen in a method for forming a memory cell. A storage element of the memory cell is formed. A read port of the memory cell is defined by forming a first transistor having a first gate coupled to the storage element, a first source region, and a first drain region; and forming a second transistor having a second gate, a second source region coupled to the first drain region, and a second drain region. Forming the first and second transistors includes forming a first dopant profile in the first and second source regions, and forming a second dopant profile in the first and second drain regions that is asymmetric with respect to the first dopant profile.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"The disclosed subject matter will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:
"FIG. 1 is a diagram of a memory cell with an asymmetric read port in accordance with one aspect of the present subject matter;
"FIG. 2 is an exemplary cross-section device diagram of a pull-down transistor and a pass gate transistor in the asymmetric read port of FIG. 1;
"FIG. 3 is a diagram of the read port of FIG. 2 in an earlier manufacturing stage to illustrate a method for forming the asymmetric extension regions;
"FIG. 4 is a diagram of the read port of FIG. 1 in an earlier manufacturing stage to illustrate a method for forming the asymmetric characteristics of the pull-down transistor and the pass gate transistor by varying the halo dopant profile;
"FIG. 5 is a diagram of the read port of FIG. 2 in an earlier manufacturing stage where the asymmetric halo doping also includes using different maximum implant angles in lieu of or in combination with different dopant concentrations for the source halo region and the drain halo region;
"FIG. 6 is a diagram of the read port of FIG. 2 showing both asymmetric extension regions and different strength and positioned halo regions;
"FIG. 7 is a top view of the read port illustrating the relative gate lengths of the pull-down transistor and the pass gate transistor.
"While the disclosed subject matter is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosed subject matter to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosed subject matter as defined by the appended claims."
For additional information on this patent application, see: Mojumder,
Keywords for this news article include: Electronics, Semiconductor,
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