The patent's assignee is The Regents Of The
News editors obtained the following quote from the background information supplied by the inventors: "DNA was first isolated from cells by the Swiss scientist
"In nanopore sequencing a DNA strand to be sequenced is passed through an ionic fluid filled sensor having a very small pore while a voltage is induced across the sensor. The resulting sensor current depends on the structure of the DNA strand. By analyzing the sensor current the DNA strand can be sequenced. While the theoretical framework of nanopore sequencing is well understood, prior art nanopore sequencing systems and devices were not fully developed. Nanopore sequencing currents are very small and any realistic nanopore sequencing system requires very high gains. Very high gains tend to create reading instabilities caused by distributed resistances and capacitances as well as internal and external noise.
"Despite those problems the promise of nanopore sequencing has motivated the development of electronic devices and systems that can detect and quantify individual nucleotides in a polynucleotide. In practice a nanopore sensor has two chambers, referred to as a cis and a trans chamber. Those chambers are filled with a buffered ionic conducting solution (for example, KCl) and a voltage is applied across the nanopore chambers. As a result, a charged DNA initially placed in the cis chamber starts moving towards the trans side. As it traverses the nanopore, the ionic current momentarily decreases. The ionic current is typically in the range of tens to hundreds of picoAmperes. The resulting electric current depends on the number of ions (the charge/net charge) in the nanopore as well as on the nanopore dimensions. The number and charge of ions can be the result of the DNA nucleotide strand passing through the nanopore (or approaching the nanopore opening). It is by monitoring the resulting current that the DNA nucleotide can be sequenced.
"Accurately measuring the ultra-low current variations requires a very specialized amplifier that is referred to herein as a patch-clamp. Practical patch-clamps include an input headstage current-to-voltage converter and a difference amplifier that amplifies the voltage from the headstage. A patch-clamp must meet two very challenging design requirements. First, the input-offset voltage (V.sub.OS) of the headstage must be minimized. Even the best high-gain amplifiers available have some V.sub.OS. Causes for the V.sub.OS include random process mismatches and unavoidable systematic variations. Whatever the V.sub.OS is, it is amplified by the difference amplifier. In effect the V.sub.OS limits the output dynamic range.
"Secondly, patch-clamp input parasitic capacitances have to be reduced to prevent headstage saturation. When a command voltage V.sub.CMD is applied to the nanopore sensor to produce operating currents, that voltage is actually applied through a resistance to an inverting input of an op-amp. Thus a command voltage V.sub.CMD change is time delayed due to unavoidable stray system capacitances. This causes a transient difference between the inverting input and the non-inverting input which leads to output saturation until the parasitic capacitances are charged and the inverting input once again is equal to V.sub.CMD. During this interval, known as the 'dead-time' all incoming data is lost. Minimizing V.sub.OS and compensating for input parasitic capacitances and resistance are major design problems in nanopore sequencing.
"Modern patch-clamps are rather specialized high gain, differential op-amp transimpedance amplifiers that use either resistive or capacitive feedback. FIGS. 1(a) and 1(b) present those two basic patch-clamp architectures. In any event, the basic patch-clamp comprises two components: an amplifier 10 and a compensation system that comprises either a resistor 12, reference the resistive feedback patch-clamp circuit 6 shown in FIG. 1(a), or a capacitor 14 in parallel with a reset switch 16, reference the capacitive feedback patch-clamp circuit 8 shown in FIG. 1(b). In both circuits a command voltage V.sub.CVM is applied to the non-inverting input 17 of the amplifier 10 while the potential across a nanopore sensor 302 (see for example FIG. 6) is applied to the inverting input 18.
"In FIG. 1(a), the input current I.sub.in on the inverting input 18 is amplified in accord with the value of the feedback resistor 12 (R.sub.f). The resulting transimpedance gain is simply V.sub.OUT=R.sub.f.times.I.sub.in. In FIG. 1(b), the capacitive feedback acts as an integrator, and thus the amplifier 10 must in practice be followed by a differentiator.
"In theory the basic patch-clamps 6 and 8 are sound. In practice, things go wrong. Transimpedance patch-clamp amplifiers that use resistive feedback, reference FIG. 1(a), suffer from significant time delays following command voltage V.sub.CMD changes. Referencing the nanopore sensor 302 shown in FIG. 6, those delays are a result of result of a pole-zero characteristics, the relatively large feedback resistor 12 (see FIG. 1(a)), an unavoidable series resistance R.sub.S 303, the nanopore sensor 302 capacitance (C.sub.N) 305, and the nanopore sensor 302 resistance (R.sub.N) 307. The resistive feedback patch-clamp circuit 6 shown in FIG. 1(a) operates as a non-inverting amplifier with a gain of (1+C.sub.N/C.sub.P) just after the command voltage V.sub.CMD changes. Since C.sub.N is always larger than C.sub.P the output of the amplifier 10 becomes saturated and data is lost until the amplifier 10 has time to supply sufficient charge to the capacitances to allow a return to normal operation. That 'dead-time' is very undesirable.
"In the prior art, complicated compensation circuitry has been used to attempt to avoid, shorten, or at least minimize dead-time. Such prior art compensation circuitry not only increased the complexity of the basic patch-clamp but resulted in an increased input capacitance which not only limited the bandwidth of resistive feedback patch-clamp circuits, such as the resistive feedback patch-clamp circuit 6, but usually resulted in output voltage 'ringing' in response to a step input.
"The capacitive feedback patch-clamp circuit 8 shown in FIG. 1(b) was developed at least in part to avoid the dead-time and system complexity of resistive feedback patch-clamp circuits 6 (see FIG. 1(a)). The capacitive feedback patch-clamp circuit 8 has a wide bandwidth and effectively a unity gain at the instant when the reset switch 16 is closed. By properly timing the closing of the reset switch 16 across the capacitor 14 having a capacitance of C.sub.f, a command voltage V.sub.CMD change on the non-inverting terminal 17 does not initially affect the output of the amplifier 10 and output saturation is avoided.
"Unfortunately, when the reset switch 16 opens, the input capacitance at the inverting input 18 increases by C.sub.f.times.(1+A.sub.0), wherein A.sub.o is the gain of the amplifier 10, reference the well-known Miller's theorem. That rather dramatic input capacitance change subsequently restricts the bandwidth of the capacitive feedback patch-clamp circuit 8. Thus using capacitive feedback transimpedance amplifiers makes it very difficult to apply arbitrary command voltage V.sub.CMD changes because the reset frequency (f.sub.RST) is determined by I.sub.in/(C.sub.f.times..DELTA.V), where .DELTA.V is the voltage difference between the inverting input 18 and the output voltage V.sub.O. That frequency is not necessarily synchronized with command voltage V.sub.CMD changes.
"One solution to the reset frequency-command voltage V.sub.CMD change problem is to simply increase the reset frequency (f.sub.RST) by decreasing the capacitance C.sub.f of the capacitance 14 so that the reset frequency is compatible with the command voltage V.sub.CMD changes. This requires multiple capacitors and their proper selection as feedback capacitor 14 capacitances whenever waveforms having different transition periods are applied as the command voltage V.sub.CMD changes. The result is a much larger and more complex patch-clamp amplifier.
"Prior art compensation of patch-clamp amplifiers used additional amplifiers to estimate series resistance (R.sub.S) and parasitic capacitance (C.sub.P), a rather complex circuit resulted.
"Therefore, a new patch-clamp amplifier circuit that avoids the foregoing and other limitations in the prior art would be desirable. Even more desirable would be new patch-clamp amplifier systems that incorporate compensation tailored to the particular application. Ever more beneficial would be new patch-clamp systems having compensation that can be digitally controlled."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The principles of the present invention provide for techniques for patch-clamp amplifier circuits that incorporate compensation and that can be tailored to a particular application. The new patch-clamp circuit uses digitally controlled compensation and can be used in a nanopore sequencer for sequencing polynucleotides.
"Those principles are incorporated in a patch-clamp circuit having a clock that produces timing signals. The patch-clamp circuit further includes a differential amplifier circuit having a non-inverting input, an inverting input with a parasitic capacitance and an electrode resistance, and an output. A feedback resistor is connected between the output and the inverting input. A reset switch receives the timing signals and in response selectively connects the output to the inverting. A command voltage circuit receives command voltages and timing signals. The command voltage circuit produces stepped command voltages that are applied to the non-inverting input in response to the timing signals. A sensor having an input capacitance and a series resistance is operatively connected to the inverting input. The reset switch closes for a time TR in synchronization with step changes in the stepped command voltages and then opens. The time TR is sufficient to prevent saturation of the differential amplifier circuit during the step changes but without blanking out the stepped voltage. The stepped command voltages are selected to compensate for the series resistance and the electrode resistance so as to produce predetermined voltages across the sensor.
"In practice the patch-clamp system uses a nanopore sensor while the differential amplifier circuit can have a current to voltage converter and a difference amplifier. The command voltage circuit may be a sample and hold circuit, a Digital-to-Analog converter or some other type of circuit that produces well defined steps. In practice the output can be applied to an Analog-to-Digital converter that produces an amplified digital version of the current in the sensor. The digital version can be applied to a field programmable array or otherwise input into a computer. Preferably that computer causes the command voltages to be applied to the command voltage circuit.
"The principles of the present invention also enable methods of compensating sensors used in patch-clamp systems. Such a method involves connecting a first end of an electrode to the inverting input of a patch-clamp system, connecting the second end of the electrode to ground, and connecting a feedback resistor R.sub.F between the inverting input and the output of the patch-clamp system. This enables obtaining a steady state output from the patch-clamp system. A step voltage is then applied to the non-inverting input of the patch-clamp system. The output voltage variation of the patch-clamp system converter in response to the step voltage is then obtained and from that output voltage variation; the series resistance R.sub.E of the electrode can be determined. After the series resistance is determined a sensor is connected between the second end of the electrode and ground. The steady state output of the patch-clamp system is then found and the sensor current is measured. The sensor series resistance R.sub.S can then be determining from the measured sensor current i, the series resistance R.sub.E, and the steady state output. Once the series resistance R.sub.E is known, a predetermined voltage can be applied across the sensor by applying a compensated voltage to the non-inverting input, where the compensated voltage is equal to the predetermined voltage plus the sensor current i times the series resistance R.sub.S.
"In addition to compensating for resistances, the present invention can also be used to determine parasitic capacitances. To do so, after the sensor series resistance R.sub.S has been determined the patch-clamp system is set up to produce a steady state response. A compensation step voltage is then applied to the non-inverting input of the patch-clamp system. The time constant of the output is then found. The input parasitic capacitance is then determined using the previously obtained sensor series resistance R.sub.S and the time constant.
"The principles of the present invention further enable new, useful, and non-obvious nanopore sequencers. Such a nanopore sequencer includes a nanopore sensor having an input resistance R.sub.N and an input capacitance C.sub.N. The nanopore sequencer further includes a patch-clamp circuit having a non-inverting input, an inverting input having a parasitic capacitance C.sub.P, and an output. An electrode having an electrode series resistance R.sub.E connects the nanopore sensor to the inverting input. A feedback resistor having a value R.sub.F is connected between the output and the inverting input. The reset switch receives timing signals that cause the reset switch to selectively connect the output to the inverting input. A digital-to-analog circuit receives timed digital command voltages and applies stepped command voltages to the non-inverting input in response to the timed digital command voltages. The reset switch closes for a time T.sub.R in synchronization with step changes in the stepped command voltages and then opens. T.sub.R is selected to be sufficient to prevent saturation of the patch-clamp circuit without blanking out the stepped voltage. The stepped command voltages are selected to compensate for the nanopore resistance R.sub.N and the electrode series resistance R.sub.E so as to produce a predetermined voltage across the nanopore sensor.
"The nanopore sensor may comprise a semi-conductive material or it may be a cell membrane. The patch-clamp circuit may include a current-to-voltage converter and a difference amplifier. The output is beneficially applied to an analog-to-digital converter that produces an amplified digital version of the current in the nanopore sensor. That amplified digital version can be input to a field programmable array and/or as an input to a computer. Preferably the computer operatively produces the timing signals and the timed digital command voltages.
BRIEF DESCRIPTION OF THE DRAWINGS
"The advantages and features of the present invention will become better understood with reference to the following detailed description and claims when taken in conjunction with the accompanying drawings, in which like elements are identified with like symbols, and in which:
"FIG. 1(a) is a schematic depiction of a prior art resistive feedback patch-clamp circuit;
"FIG. 1(b) is a depiction of a prior art capacitive feedback patch-clamp circuit;
"FIG. 2 is a schematic depiction of a simplified compensated patch-clamp circuit in accord with the principles of the present invention;
"FIG. 3(a) is a schematic depiction of the operation of the compensated patch-clamp circuit shown in FIG. 2 when reset switch 16 is closed;
"FIG. 3(b) is a schematic depiction of the operation of the compensated patch-clamp circuit shown in FIG. 2 when reset switch 16 is open;
"FIG. 4 is a schematic depiction of a compensated patch-clamp circuit in accord with the principles of the present invention that uses a digital-to-analog converter (DAC);
"FIG. 5 illustrates a schematic depiction of a prior art patch-clamp system and a nanopore sensor;
"FIG. 6 is a schematic depiction of a preferred embodiment compensated patch-clamp circuit;
"FIG. 7 is a schematic depiction of a simplified version of the compensated patch-clamp circuit shown in FIG. 6 during early resistor compensation operations;
"FIG. 8 is a schematic depiction of a simplified version of the compensated patch-clamp circuit shown in FIG. 6 during later resistor compensation operations;
"FIG. 9 is an operational flow diagram for compensating nanopore sensor resistances;
"FIG. 10 is an operational flow diagram for compensating nanopore sensor capacitances;
"FIG. 11 is a schematic depiction of a simplified preferred embodiment compensated patch-clamp circuit during capacitor compensation; and
"FIG. 12 is a schematic depiction of a simplified preferred embodiment compensated capacitor patch-clamp circuit.
"FIG. 13 shows a three terminal nanopore sensor front end for practicing the present invention."
For additional information on this patent application, see: Dunbar, William; Kim, Jungsuk; Pedrotti, Kenneth. Compensated Patch-Clamp Amplifier for Nanopore Polynucleotide Sequencing and Other Applications. Filed
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