The patent's inventor is Youn, Tae Un (Chungcheongbuk-do, KR).
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates generally to a semiconductor memory device and a method of fabricating the same, and more particularly relates to a semiconductor memory device capable of inhibiting generation of etching damage caused during a process of fabricating a semiconductor memory device, and a method of fabricating the same.
"In semiconductor memory devices, a flash memory device comprises a plurality of strings. In each string, memory cells are disposed in serial. The string is formed on an active region, and an isolation layer is formed between the strings so that the strings are electrically isolated from each other.
"A method for fabricating a flash memory device is illustrated in detail as follows.
"On a semiconductor substrate, a gate insulating layer, a first conductive layer to be used for forming a floating gate, a dielectric layer, a second conductive layer to be used for forming a control gate and a gate mask pattern are sequentially formed. An etching process is performed according to the gate mask pattern to form an isolation trench on the semiconductor substrate. In particular, in the etching process performed for forming the trench, side walls of the first conductive layer and the gate insulating layer are exposed so that an etching damage can be generated.
"In addition, after the trench is formed, an oxidation process can be performed for compensating for etching damage in the trench. At this time, a 'bird's beak' phenomenon, in which the thickness of both ends of the exposed gate insulating layer is increased, can be generated."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "In the present invention, when a process for forming an isolation trench is performed, a first conductive layer to be used for forming a floating gate is patterned to form a first conductive pattern, a protective layer is then formed along surfaces of the first conductive pattern and an exposed gate insulating layer, and therefore the side walls of the first conductive layer can be protected by the protective layer during the subsequent etching process. In addition, since the gate insulating layer is formed such that a width of the gate insulating pattern is wider than that of the first conductive pattern, it is possible to compensate a defect caused by an excessive oxidation generated at both ends of the gate insulating layer during the subsequent etching process.
"A method of fabricating a semiconductor memory device according to an embodiment includes: sequentially forming a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer along surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench; the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer along surfaces of the isolation layer, the protective pattern and the first conductive pattern.
"Sequentially forming the gate insulating layer and the first conductive pattern on the semiconductor substrate can include forming a gate insulating layer on the semiconductor substrate; forming a first conductive layer on the gate insulating layer; and patterning the first conductive layer to form the first conductive pattern on the gate insulating layer.
"The first conductive layer is preferably formed by laminating sequentially an undoped polysilicon layer and a doped polysilicon layer. The second conductive layer is preferably formed of a doped polysilicon layer.
"The protective layer preferably is formed of a nitride layer, which can be formed through a deposition process or a nitrification process. For example, the protective layer preferably has a thickness in a range of about 50 .ANG. to about 100 .ANG..
"The method of fabricating a semiconductor memory device can further include performing an oxidation process to compensate for damage to a surface of the trench after the trench is formed.
"Etching the isolation layer is preferably performed through an etching process so as to prevent the gate insulating layer from being exposed.
"Removing the protective pattern above a surface of the isolation layer is preferably performed by a dry etching process or a wet etching process. For example, the wet etching process can be performed by utilizing phosphoric acid (H.sub.3PO.sub.4) solution as the etchant.
"A semiconductor memory device according to an embodiment includes a semiconductor substrate on which an active area and a trench are formed; a gate insulating pattern formed on the active area; a first conductive pattern formed on the gate insulating pattern and having a width narrower than that of the gate insulating pattern; protective patterns formed at lower ends of both side walls of the first conductive pattern to allow upper ends of both side walls of the first conductive pattern to be exposed; and an isolation layer formed in the trench.
"Preferably, the sum of a width of the first conductive pattern and widths of the protective patterns formed at lower ends of the side walls of the first conductive pattern is the same as a width of the gate insulating pattern.
"Also, a central portion of an upper portion of the isolation layer is located below an edge portion of an upper portion of the isolation layer.
"The semiconductor memory device further preferably includes a dielectric layer formed along surfaces of the isolation layer, the protective pattern and the first conductive pattern; and a second conductive layer formed on the dielectric layer."
For the URL and additional information on this patent, see: Youn, Tae Un. Semiconductor Memory Device and Method of Fabricating the Same. U.S. Patent Number 8618596, filed
Keywords for this news article include: Electronics,
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