The patent's inventors are Suto, Kenta (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a layout technique of semiconductor integrated circuits, and particularly to a technique which is effective when applied to the circuit design of portable devices such as a cellular phone and a Personal Digital Assistant (PDA).
"In the circuit design of portable devices such as a cellular phone and a PDA for which demand is increasing recently, reduction of power consumption has become essential. The technique of dividing a logical block on a chip into several groups and performing ON/OFF control of power source for each group is effective in reducing power consumption. A group of logical blocks operating at a single power source voltage level is referred to as the 'power domain', and a physical placement area of the logical block operating at the single power source voltage level is referred to as the 'voltage island'.
"Japanese Patent Laid-Open No. 2008-176486 (Patent document 1) describes a method of generating a voltage island at an operation synthesis level or a function design level such as Register Transfer Level (RTL). According to Patent document 1, area, timing and power consumption are estimated at the function design level and the voltage island is generated based on the estimated value. In improving timing violation or reducing area at the function design level, improvement is attempted by assigning a higher value to the power source voltage value. In addition, in reducing power consumption, improvement is attempted by assigning a smaller value to the power source voltage. A voltage island is generated, and the influence by the provision of the voltage island is fed back to the operation synthesis process. Accordingly, a circuit which has been optimized in terms of timing, area, and power consumption can be obtained in a short period."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The multi power source design approach, which optimizes power consumption of the circuit, can be mentioned as an approach of power consumption design for a semiconductor integrated circuit. The multi power source design approach uses the power-off technique, multi power source technique, and Dynamic Voltage Frequency Scaling (DVFS: substrate bias control) technique. According to the power-off technique, the power source of an unused logical block (simply referred to as 'block') is temporarily turned off to reduce leakage current. Although a circuit which performs ON/OFF control of the power source is required in the power-off technique and it is necessary to insert a level shifter between the wirings connecting blocks having low power source voltages to blocks having high power source voltages in the multi power source technique, which may lead to an overhead in the circuit, they exhibit a very large effect of reducing power consumption owing to the ability of supplying an optimal power source voltage to individual blocks in operation. According to the multi power source technique, a plurality of power source voltages with different voltage levels is generated and the optimal power source voltage is assigned to individual blocks. According to the DVFS technique, the power source voltage and operating frequency are lowered when the load to be processed is light, and then power consumption is reduced.
"However, the technique of supplying the optimal power source voltage to individual blocks in operation is not automated although the technique related to power-off, multi power source, and DVFS technique are used, and thus the conventional multi power source design method must rely on manpower (manual labor of the designer). Optimizing the power domain may be inadequate, depending on the designer's skill.
"Patent document 1 describes a proposal about multi power source, without taking into consideration power-off and DFVS. In addition, patent document 1 describes no automating generation of a power domain which is a logic level of a voltage island. Furthermore, patent document 1 describes no generation of a power domain considering the physical placement of a block either.
"The present invention has been made in view of the above circumstances and provides a technique to automatically generate a power domain.
"The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.
"The following explains briefly the outline of a typical invention among the inventions disclosed in the present application.
"A computer performs a function simulation process for evaluating whether or not a designed circuit satisfies a specification, and a clustering process which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process.
"The following explains briefly the effect acquired by the typical invention among the inventions disclosed in the present application.
"A technique for automatically generating a power domain can be obtained."
For the URL and additional information on this patent, see: Suto, Kenta; Shibatani, Satoshi; Ishikawa, Ryoji; Saito, Ken; Inoue,
Keywords for this news article include: Semiconductor,
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