Patent number 8621412 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates generally to electronic design techniques used for designing integrated circuits, and in particular to methods and mechanisms for optimizing the design flow used to process integrated circuit designs.
"The design of complex and high performance integrated circuits requires a considerable investment of time and cost. Typically, designers of integrated circuits follow multiple steps and use multiple software design tools to create a fabricated chip. Initially, the designer may use a hardware description language (HDL), such as Verilog or VHDL, to describe the original design. Then, the design may be synthesized by a synthesis tool into the logic needed to implement the desired logical functionality of the design. This may be followed by the generation of a description at the transistor and circuit component level. The next step may be the layout step where the circuit elements are placed within the overall circuit. Then, following the layout step, the wiring between the placed circuit elements may be arranged and routed.
"When designing an integrated circuit, this design flow may be traversed hundreds of times or more from start to finish. After each pass through the design flow, simulations may be run on the placed and routed design to evaluate its performance. The design may need to meet various predetermined performance goals, including desired clock speed and power consumption. Additionally, any flaws or undesired behavior may be corrected by making changes to the design and then making another pass through the design flow.
"As the design is nearing completion, typically only minor changes are made to the design for each iteration. However, a drastically different placement and routing of the design may be produced by the tools of the design flow even for small changes to the design. As such, the results of the implementation tools of a slightly different version of the design do not leverage the results of the previous version of the design. Therefore, there may not be any significant improvement in the quality of results or execution time from one design version to another. This may be undesirable when the design is fairly convergent and performing close to the desired result. Such unpredictability in the place and route construction and quality of results can have a negative impact on tight time to market schedules."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In one embodiment, a previous best place-and-route run result may be used to generate a detailed set of physical region constraints (or micro-regions) of the placement of all sequential elements in the design. The micro-regions may be generated at a user specified level of granularity. The micro-region based physical constraints may then be fed into the next place-and-route construction build along with the register-transfer level (RTL) definition of the design and other physical updates, such as pin locations, I/O timing constraints, etc.
"In one embodiment, micro-region constraints may be provided to a placement tool. The placement tool may be any type of placement tool that is part of a design flow, such as a synthesis and placement tool, place and route tool, or other tool. The design flow may include multiple tools for processing the digital design of the integrated circuit.
"In one embodiment, the micro-region constraints may be based on a previous run of the design through the design flow. In a typical scenario, the previous run through the design flow may have produced a fairly convergent design. The RTL definition of the design may have changed slightly from the previous run, and instead of starting a completely new run through the design flow, which may produce materially different results, the micro-region constraints may provide the next run with a starting point that allows some flexibility to the tools but prevents a completely differently design layout from being generated.
"In one embodiment, in order to generate the micro-region constraints, a grid may be overlaid on top of the place-and-route result of the previous design flow. The grid may be rectangular and may partition the chip design layout into a plurality of micro-regions. In one embodiment, the layout of the micro-regions on top of the place-and-route result may be user configurable. For example, the user may select the number of micro-regions in the grid. Alternatively, the micro-regions may be automatically selected via a software program that bases its decisions on the design and the changes that were made after the previous run through the design flow.
"In one embodiment, after the design is partitioned into a plurality of micro-regions, the sequentials that reside within each micro-region may be recorded. Then, sequentials that belong to a given micro-region may be forced to stay in that given micro-region on the next run through the design flow. In some embodiments, each micro-region may be defined as one of a plurality of types of micro-regions. For example, in one embodiment, the different types of micro-regions may be guides, inclusive, and/or exclusive. The classification of micro-regions may be automatically chosen by software or manually chosen, depending on the embodiment. Similarly, the sizes of micro-regions may be automatically chosen by software or manually chosen, depending on the embodiment.
"In one embodiment, changes may be made to the design after the previous best run through the design flow. The changes may be made for various reasons, and the changes may be to the physical design and/or may be changes to the constraints provided to the tools of the design flow. In one embodiment, a script may be utilized, and the script may compare the current RTL of the design to the RTL of the previous iteration of the design. The script may determine in which modules the changes fall, and then the modules may be mapped to their locations within the most recent iteration of the placement results. Then, when specifying the micro-regions, the areas with the most changes may be given larger micro-regions to give the placement tool(s) more flexibility to find the optimum placement of the sequentials in these areas. For the areas that are predominately the same, the micro-regions may be made smaller to lock in the previously generated layout. Furthermore, the type of micro-region used for a specific area in the design may be based on the amount of changes in that area.
"A micro-region specification may be generated based on the partitioning of the design and the sequentials that belong to each micro-region. Then, the micro-region specification may be fed as a constraint into one or more placement tools within the design flow. The specification may be a seed for each placement tool, and the placement tool may use the specification to determine how to place the sequentials within the layout. For example, in one embodiment, any guide micro-regions may be considered recommendations, and the tool may attempt to place the sequentials in their assigned micro-region. Inclusive micro-regions may prevent sequentials from leaving their assigned micro-region but may allow other, external sequentials to be placed in the micro-region. Exclusive micro-regions may prevent sequentials from entering or leaving the micro-region, such that the sequentials that were in the micro-region in the previous layout may remain in the micro-region for the current layout.
"These and other features and advantages will become apparent to those of ordinary skill in the art in view of the following detailed descriptions of the approaches presented herein."
URL and more information on this patent, see: Vats, Suparn; Mylius, John H.; Rajagopal, Karthik. Micro-Regions for
Keywords for this news article include: Software,
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC
Most Popular Stories
- Dmytro Firtash, Ukrainian Billionaire, Arrested in Vienna
- Obama, Ukraine Discuss Russian Incursion in Crimea
- Obama's Overtime Initiative Praised, Condemned
- Koch Brothers Step up Anti-Obamacare Campaign
- Republicans Warn Obama on Immigration
- Liberty Media Drops Sirius Bid
- FDIC Sues Big Banks Over Rate Manipulation
- Uli Hoeness, Bayern Munich President, Gets Prison for Tax Evasion
- Calumet Photo Files for Bankruptcy
- West Readies Harsh Sanctions Against Russia