Patent Issued for Method of Selecting a Set of Illumination Conditions of a Lithographic Apparatus for Optimizing an Integrated Circuit Physical Layout
Patent number 8621401 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "An integrated circuit has circuit functionality that is determined by the geometrical layout of its constituting complex circuit elements, formed as polygons or polygon structures, which are arranged in layered structures of various materials, such as polysilicon (poly), silicon dioxide, doped regions, dielectrics and metal regions. Examples of complex circuit elements are: FET (Field Effect Transistor), BJT (Bipolar Junction Transistor), diodes with various functional goals, resistor, inductor, capacitor, interconnect to connect various passive and active elements with desired goals and configuration etc. Further, any possible circuit configurations formed from combination of such elements from a single device such as a transistor to matched transistor pairs, transistors on critical timing paths, decoupling capacitor/coupling inductor to more complex configurations such as clock trees, sense amplifiers, IO drivers, row/column decoder of a memory, current mirrors, temperature sensor, PLL, DLL & whole memory arrays are considered complex circuit elements. In short, these elements have a recognized and predefined electrical function in an electrical circuit scheme, and thereby constitute the active and passive elements of the electrical circuits that are defined by the polygon structures. Generally, the circuit layout is provided as a mask layout of a mask element in a photolithographic apparatus. The mask layout can comprise geometric adaptations to optically correct for proximity effects which take place during optical transfer in the lithographic apparatus, for instance, by a lens system and/or projection system. These optical transfer systems have specific optical characteristics that can be tuned to provide an optimal setup of lithographic tunic parameters. The parameters may sometimes even be associated to a specific circuit layout requiring specific setup of the lithographic apparatus. In addition, the lithographic system has certain optical system deficiency characteristics (lens aberration etc) that can be accounted for in the optical proximity corrections carried out in the circuit layout.
"Since the mask layout is often tuned to the specific lithographic system, it will result in printing difficulties when the illumination parameters are not carefully selected. This is especially true when a manufacturer chooses to change the lithographic systems. Accordingly, the objective is to select a set of illumination conditions in a lithographic apparatus, in a process for transferring a pattern to a target substrate, to an extent that acceptable transfer characteristics are achieved which will result limited production loss of malfunctioning circuits. Generally, throughout this text, by optimizing the illumination conditions it is sought to optimize lithographic process parameters relevant for obtaining correctly functioning integrated circuits, including but not limited to tuning parameters such as focus, dose, numerical aperture, sigma in, sigma out.
"Calculating a cost number for specific illumination settings, which cost number can be optimized to optimize to a yield prediction value, can be seen as an advanced way of identifying illumination settings for a different production setup: if the cost number is too bad one may opt to modify the illumination settings to get better manufacturing yield.
"One publication that deals with calculating a yield prediction value is U.S. Pat. No. 6,738,954. In this publication, a quality number calculation is performed on a proposed layout. A number of subdivisions of a circuit are assessed each resulting in an average fault number and a statistical error value of said fault number. Iteratively, a statistical error of the average number is reduced until the statistical error is below an error limit.
"U.S. Pat. No. 7,013,441 is another publication that is concerned with calculating a predicted manufacturing yield from an integrated circuit. Here, by selecting library elements from a design database to include in a proposed design for the integrated circuit, a yield is calculated based on a normalization factor that is associated to the library element and used to account for a sensitivity of the library element to a given defect.
"U.S. Pat. No. 7,245,356 concerns a method of configuring a transfer of an image of a patterning device pattern. A pattern, representative of an aggressive configuration included in the mask layout is selected to optimize the parameters of the lithographic apparatus. A simulation model is provided that simulates a transferred image, to identify a response of the illumination system for a number of individual source points, which results in a determination of an optimal illumination arrangement."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "It is desirable to provide a further optimization in a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. According to an aspect of the invention, there is provided a method according to claim 1. In particular, according to said aspect, there is provided a method including providing an initial set of illumination conditions; providing a plurality of polygon patterns requiring illumination conditions critical for circuit functionality; calculating for the initial set of illumination conditions a local cost number, defining a difference measure of at least one critical dimension between the polygon pattern and a transferred polygon pattern as a function of illumination condition; aggregating for each polygon pattern the cost numbers; and varying the illumination conditions so as to select an optimal set of illumination conditions having an optimized aggregated cost number. The method further comprises identifying polygon patterns as predefined complex circuit elements wherein the cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit element design intent. In another aspect there is provided a system according to claim 12. The system comprises an input, an output and a processor arranged to perform the method of claim 1.
"In yet another aspect, there is provided a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate, the layout comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other, the method comprising: providing an initial set of illumination conditions; providing a plurality of polygon patterns requiring illumination conditions critical for circuit functionality; calculating for the initial set of illumination conditions a local cost number, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition; aggregating for each polygon pattern the cost numbers; and varying the illumination conditions so as to select an optimal set of illumination conditions having an optimized aggregated cost number, wherein the method further comprises: selecting a cost number function to have interdependencies in at least two critical dimensions of the polygon pattern, so as to express two dimensional pattern geometry."
URL and more information on this patent, see: Berkens,
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