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Researchers Submit Patent Application, "Power and Pin Efficient Chip-To-Chip Communications with Common-Mode Rejection and SSO Resilience", for...

February 6, 2014



Researchers Submit Patent Application, "Power and Pin Efficient Chip-To-Chip Communications with Common-Mode Rejection and SSO Resilience", for Approval

By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Cronie, Harm (Lausanne, CH); Shokrollahi, Amin (Preverenges, CH), filed on September 16, 2013, was made available online on January 23, 2014.

The patent's assignee is Ecole Polytechnique Federale de Lausanne (EPFL).

News editors obtained the following quote from the background information supplied by the inventors: "When an electronic device contains more than one integrated circuit ('IC'), signals typically need to be conveyed from chip to chip over a communication bus. Communication may also take place over a communication bus between two ICs that are part of two different devices. In either case, the communication bus might comprise one or more wires. The ICs might be mounted on a printed circuit board ('PCB') with the wires being striplines or microstrips. For communication between devices or boards, the wires might be the copper wires of a cable or optical fibers connecting the devices/boards. As is well known, the communication requires electrical energy and can generate electrical noise and errors can occur when the conditions of communication are not ideal.

"For an increasing number of applications, the speed of the communication bus is a limiting factor. One way to increase the speed is to increase the number of wires that make up the bus. However, this also increases the number of pins of the ICs that are needed and many times, IC pins are a scarce resource. Another limiting factor is the power consumption of the bus and the circuitry driving the bus. Simply increasing the transmit power might not result in a better performance of the bus, because that might increase the amount of noise and lower performance.

"Signals transmitted on a communication bus are subjected to several types of noise. One source of noise is thermal noise that can be modeled as independent Gaussian noise. The resilience against Gaussian noise can be improved by increasing signal swings or by the use of well-designed signaling schemes. Another type of noise is interference that may result from neighboring wires of the communication bus. Some noise and interference has a component that is common to the several wires of the bus and this noise is called common-mode noise. Another source of noise is simultaneous switching output ('SSO') noise that is caused by a bus driver current that varies in time. SSO noise can cause major problems in modem high-speed bus communication systems. Yet another source of noise is crosstalk noise, which is caused by interference of the signals on the different wires of the same bus. Crosstalk noise is one of the main sources of noise for high-frequency buses and is hard to eliminate by just increasing the energy of the signals on the bus, since an increase of energy leads directly to an increase of interference to nearby wires on the bus, and will lead to even worse crosstalk noise.

"There are several approaches to signaling for chip-to-chip communications that may address one or more of the above constraints.

"One approach is single-ended signaling where an information-carrying signal is transmitted on a single wire with respect to a common reference. Although single-ended signaling is efficient in terms of the number of wires used, it is susceptible to common-mode noise and it introduces SSO noise. Furthermore, for the detection of a single-ended signal, a reference is required at the receiver. Inaccuracies in the generation of the reference signal lead to higher error rates of the communication system. Hence, a signaling method that does not require a reference is preferred over a signaling method that does require one. Single-ended signaling is also not very efficient in terms of transmission power that is required to achieve certain Gaussian noise resilience, and it is also not efficient in terms of crosstalk noise.

"Another signaling method is differential signaling. In differential signaling, an information-carrying signal is transmitted on a pair of wires. The original information-carrying signal is encoded into the difference between the signals transmitted on the pair of wires. The advantage of differential signaling is that it rejects noise that is common on both wires.

"For chip-to-chip communications, the information-carrying signal is often a non-return-to-zero ('NRZ') encoded signal and, as such, differential signaling does not introduce SSO. Another advantage is that differential signaling is less sensitive to interference and crosstalk. The reason for this is interference and crosstalk mainly couple into the common mode and are cancelled at the receiver. Moreover, in terms of resilience against Gaussian noise, differential signaling is more power-efficient compared to single-ended signaling. The main disadvantage of differential signaling is that it uses twice the number of pins compared to differential signaling.

"The ratio between the number of bits transmitted in a cycle of time T and the number of bus wires is referred to as the pin efficiency of the bus. While communication buses based on differential signaling provide good noise resilience, their pin efficiency is low. Differential signaling is more power efficient than single-ended signaling but still a substantial amount of the power consumption of a bus communication system is used in the drivers of the bus wires.

"One approach to addressing this issue is explained in Cronie I, which describes a method for bus communication that achieves a higher pin-efficiency than differential signaling while using less transmit power and provides resilience to common-mode noise and SSO noise. One approach described therein, referred to as 'Orthogonal Differential Vector Signaling' or 'ODVS', achieves a pin-efficiency that is close to one when the number of wires is large. In some applications, it is preferable to increase the noise resilience of a communication system as described above at the expense of the pin-efficiency.

"Cronie II teaches a method referred to as 'Coded Differential Vector Signaling' or 'COVECS' that uses methods of forward error correction to use some of the pins saved by ODVS to increase the noise resilience.

"While the methods of Cronie I and Cronie II offer substantial improvements regarding the tradeoff of pin-efficiency and noise resilience as compared to other approaches, there are some applications wherein additional improvements are possible. For example, since embodiments of ODVS might use a number of wires that are a power of two, applications where that is not a convenient number of wires might need another approach.

"With the methods of Cronie II, improving the noise resilience of the system might use up a significant number of pins saved by ODVS and the circuitry needed for encoding and decoding according to the teachings of Cronie II may be complex and may not be applicable in situations where the data transfer is of very high rate, thus requiring another approach.

"Another application is where the pin-efficiency needs to exceed one. What is needed is a method that provides a wider range of possible pairs of pin-efficiency and noise resilience, allows for very efficient encoding and decoding, and leads to new tradeoffs between pin-efficiency and noise resilience."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In methods and apparatus for bus communications according to aspects of the present invention, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

"In an specific embodiment, the spherical code is a sparse permutation modulation code and the operation of mapping the first set of physical signals to a codeword of the permutation modulation code further comprises accessing a storage location for a generating vector, selecting a distinguished position of the generating vector of the permutation modulation code, mapping the first set of physical signals to a first sequence of bits, subdividing the first sequence of bits into a second sequence of bits and a third sequence of bits, comparing the second sequence and the third sequence and putting a first predetermined value into the distinguished position of the generating vector if the second sequence and third sequence satisfy a predetermined relation, and putting a second predetermined value into a second position of the generating vector different from the distinguished position, wherein the second position is obtained from the second sequence using a predetermined process, when the second sequence and third sequence do not satisfy the predetermined relation, putting a first predetermined value into a first position of the generating vector obtained from the second sequence, and putting a second predetermined value into a second position of the generating vector obtained from the third sequence, and putting a third predetermined value into all the positions of the generating vector that are not equal to the first position or the second position.

"The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 illustrates an environment in which the present invention might be used.

"FIG. 2 is a schematic diagram illustrating the communication bus of FIG. 1 in greater detail.

"FIG. 3 is a schematic diagram illustrating the environment of FIG. 1 wherein a vector signal encoder and a vector signal decoder are used.

"FIG. 4 is a signal plot illustrating a signaling scheme that might be used on the bus lines of FIG. 3.

"FIG. 5 is a block diagram illustrating the vector signal decoder of FIG. 3 in greater detail.

"FIG. 6 is a block diagram illustrating the vector signal encoder of FIG. 3 in greater detail.

"FIG. 7 is a block diagram illustrating functionality of the code map unit of FIG. 6.

"FIG. 8 is a block diagram illustrating functionality of an alternative code map unit that can be used in the vector signal encoder of FIG. 6.

"FIG. 9 provides examples of spherical codes as might be used by the code map unit of FIG. 7; FIG. 9a gives an example of spherical codes in three dimensions and size 8; FIG. 9b gives an example of spherical codes in three dimensions and size 16.

"FIG. 10 is a block diagram illustrating functionality of the transform unit of FIG. 6.

"FIG. 11 is an illustration of an example Hadamard matrix that might be used by the transport unit of FIG. 10.

"FIG. 12 is a block diagram illustrating an embodiment of the vector signal encoder of FIG. 3 in greater detail.

"FIG. 13 is a flowchart of an example encoding process for encoding input bits into a vector signal that can be used on the communication bus.

"FIG. 14 is a flowchart of another example encoding process for encoding input bits into a vector signal that can be used on the communication bus.

"FIG. 15 is a flowchart of an example of a lower pin-efficiency encoding process for encoding input bits into a vector signal that can be used on the communication bus.

"FIG. 16 is a flowchart of another example of a lower pin-efficiency encoding process for encoding input bits into a vector signal that can be used on the communication bus.

"FIG. 17 is a flowchart illustrating an encoding process for a PM code.

"FIG. 18 is a chart of values that might be stored in memory or generated in various steps of the process illustrated in FIG. 17, for various example inputs.

"FIG. 19 is a flowchart illustrating a demodulating process for a PM code.

"FIG. 20 is a flowchart illustrating a decoding process for a PM code.

"FIG. 21 is a table of values that might occur during the decoding process of FIG. 20.

"FIG. 22 illustrates an encoding procedure for sparse PM codes; in the procedure of FIG. 22a, the number n is not a power of 2, and m is chosen such that 2 m-1
"FIG. 23 illustrates a decoding procedure for sparse PM codes, wherein the number n is assumed to not be a power of 2, and m is chosen such that 2 m-1
"FIG. 24 illustrates a decoding procedure for sparse PM codes, wherein the number n is assumed to be a power of 2, and m is chosen such that n=2 m+1.

"FIG. 25 is a table of values that might be used for sparse PM coding.

"FIG. 26 is a block diagram illustrating an embodiment of the vector signal encoder of FIG. 3 that uses multilevel PM codes."

For additional information on this patent application, see: Cronie, Harm; Shokrollahi, Amin. Power and Pin Efficient Chip-To-Chip Communications with Common-Mode Rejection and SSO Resilience. Filed September 16, 2013 and posted January 23, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3423&p=69&f=G&l=50&d=PG01&S1=20140116.PD.&OS=PD/20140116&RS=PD/20140116

Keywords for this news article include: Ecole Polytechnique Federale de Lausanne (EPFL).

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Source: Politics & Government Week


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