The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "NAND flash memory, as well as other types of non-volatile memories ('NVMs'), are commonly used for mass storage. For example, consumer electronics such as portable media players often include raw flash memory or a flash card to store music, videos, and other media.
"Conventional flash memory may include arrays of memory cells composed of floating gate transistors. Charge may be stored or left off of each transistor's floating gate in order to store bits of data. For example, the floating gate of a transistor may be charged to indicate a bit value of '0' or may be left uncharged to indicate a bit value of '1.' The charge or lack thereof may affect a transistor's threshold voltage, which a controller for the non-volatile memory may sense by applying a reference voltage to the transistor. Such non-volatile memories that store one bit per cell are commonly referred to as 'single-level cell' ('SLC') NVMs.
"To increase the storage capacity of a non-volatile memory while maintaining a small NVM size, some current non-volatile memories may store multiple bits of data in each memory cell by varying the amount of charge stored in the floating gate of a transistor. Such NVMs that store more than one bit per cell are commonly referred to as 'multi-level cell' ('MLC') NVMs. Since multi-level cells may have lower reliability than single-level cells, some non-volatile memories may have portions of their memory cells pre-allocated for MLC storage and other portions of their memory cells pre-allocated for SLC storage."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Systems and methods are disclosed for dynamically allocating the number of bits per cell used for memory locations of a non-volatile memory, such as flash memory. In other words, instead of a memory location being pre-allocated as an MLC or SLC location, the MLC or SLC allocation of the memory location may be made during run-time of a memory system (e.g., electronic device, memory card, or USB drive).
"In some embodiments, a memory system can include a host and a non-volatile memory ('NVM') package. The NVM package can include one or more NVM devices for storing information and may optionally include a NVM controller. The host may include a host controller for identifying a memory location in the NVM package to access and may instruct the NVM package to read data from, program data in, or erase data from the identified memory location (e.g., via the NVM controller).
"The host can further determine whether to access the memory location as a single-level cell location or multi-level cell location. For example, the host can make this determination based on the desired storage reliability, storage performance, or storage speed. Thus, the host can use any suitable number of bits per cell when accessing the memory location regardless or independently of the number of bits per cell previously used for the same memory location. In other words, after each erase cycle on the memory location, the host can newly assign the memory location as an SLC or MLC memory location based on current needs or preferences.
"In some embodiments, a host can dynamically allocate the number of bits per cell for a memory location using a portion of an address vector. The address vector can indicate the physical address of the memory location within the non-volatile memory by, for example, specifying the NVM device, the block, and page of the memory location. The address vector may also include a SLC/MLC indicator, which may indicate the number of bits per cell to use for the specified memory location. For example, in some embodiments, the SLC/MLC indicator may include one bit, where a first bit value (e.g., '0') may indicate SLC and a second bit value (e.g., '1') may indicate two-bit MLC.
"The NVM package (e.g., via an NVM controller) may access the specified memory location based on the SLC/MLC indicator included in the address vector. For example, if the SLC/MLC indicator indicates that a specified block should be accessed as an SLC block, the NVM package may program the pages of the SLC block in a SLC page programming order, and if the SLC/MLC indicator indicates that the specified block should be accessed as an MLC block, the NVM package may program the pages in the MLC block in an MLC page programming order.
"The host or the NVM package may maintain a mapping between the specified memory location and the number of bits per cell used when accessing the specified memory location (e.g., within a lookup table). This way, the memory location may be accessed using the appropriate SLC or MLC techniques during subsequent read, program, or erase operations.
BRIEF DESCRIPTION OF THE DRAWINGS
"The above and other aspects and advantages of the invention will become more apparent upon consideration of the following detailed description, taken in conjunction with accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
"FIG. 1 is a schematic view of an illustrative memory system including a host controller and a managed non-volatile memory ('NVM') package configured in accordance with various embodiments of the invention;
"FIG. 2 is graphical view of an illustrative address vector, which includes a SLC/MLC indicator portion, in accordance with various embodiments of the invention;
"FIG. 3 is a table providing an illustrative page programming order for single-level cell ('SLC') blocks and two-bit multi-level cell ('MLC') blocks in accordance with various embodiments of the invention;
"FIG. 4 is a schematic view of an illustrative memory system including a host controller and a raw NVM package configured in accordance with various embodiments of the invention;
"FIG. 5 is a flowchart of an illustrative process for dynamically allocating the number of bits per cell for a memory location of a non-volatile memory device in accordance with various embodiments of the invention;
"FIG. 6 is a flowchart of an illustrative process for storing data in a non-volatile memory using either SLC or MLC in accordance with various embodiments of the invention; and
"FIG. 7 is a flowchart of an illustrative process for reading data from a non-volatile memory using either SLC or MLC in accordance with various embodiments of the invention."
For additional information on this patent application, see: Wakrat,
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