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Patent Application Titled "Methods for Fabricating Integrated Circuits with Stressed Semiconductor Material" Published Online

February 6, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Bello, Abner (Troy, NY); Paul, Abhijeet (Albany, NY), filed on July 10, 2012, was made available online on January 23, 2014.

The assignee for this patent application is Globalfoundries Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. Such transistors may be planar or non-planar, such as finFETS. A transistor includes a gate electrode as a control electrode, and a pair of spaced apart source and drain electrodes. A control voltage applied to the gate electrode controls the flow of a drive current through a channel that is established between the source and drain electrodes.

"The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size; that is, the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to smaller minimum feature sizes, the gain of performance due to scaling becomes limited. As new generations of integrated circuits and the MOS transistors that are used to implement those ICs are designed, technologists must rely heavily on non- conventional elements to boost device performance.

"The performance of a MOS transistor, as measured by its current carrying capability, is proportional to the mobility of a majority carrier in the transistor's channel. By applying an appropriate stress to the channel of the MOS transistor, the mobility of the majority carrier in the channel can be increased which increases drive current thereby improving performance of the MOS transistor. For example, applying a compressive stress to the channel of a P-channel MOS (PMOS) transistor enhances the mobility of majority carrier holes, whereas applying a tensile stress to the channel of an N-channel MOS (NMOS) transistor enhances the mobility of majority carrier electrons. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance.

"Accordingly, it is desirable to provide improved methods for fabricating integrated circuits with stressed semiconductor material. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Methods for fabricating integrated circuits are provided. In accordance with one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first surface. In the method, a stress is applied to the semiconductor substrate to change inter-atomic spacing at the first surface of the semiconductor substrate to a stressed inter-atomic spacing. Then, the semiconductor substrate is processed. Thereafter, the stress is released and the first surface of the processed semiconductor substrate retains the stressed inter-atomic spacing.

"In another embodiment, a method for stressing a semiconductor substrate for fabrication of an integrated circuit is provided. The method includes applying a stress throughout the semiconductor substrate. While applying the stress throughout the semiconductor substrate, a stress retention layer is formed over the semiconductor substrate. Then, the stress is released.

"In accordance with another embodiment, a method for fabricating an integrated circuit provides a semiconductor substrate. A stress is applied to the semiconductor substrate to impose a stressed inter-atomic spacing therein. While applying the stress, a liner is formed over the semiconductor substrate. Then, the stress is released and the semiconductor substrate retains the stressed inter-atomic spacing through interaction with the liner.

BRIEF DESCRIPTION OF THE DRAWINGS

"Embodiments of methods for fabricating integrated circuits with stressed semiconductor material will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:

"FIGS. 1-6 illustrate, in cross section, a portion of an integrated circuit and method steps for fabricating an integrated circuit in accordance with various embodiments herein."

For more information, see this patent application: Bello, Abner; Paul, Abhijeet. Methods for Fabricating Integrated Circuits with Stressed Semiconductor Material. Filed July 10, 2012 and posted January 23, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2244&p=45&f=G&l=50&d=PG01&S1=20140116.PD.&OS=PD/20140116&RS=PD/20140116

Keywords for this news article include: Electronics, Semiconductor, Globalfoundries Inc..

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Source: Politics & Government Week


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