This patent application is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a FinFET device with a gate electrode comprised of graphene and various methods of forming such FinFET devices.
"The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region.
"To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. Due to rapid advances in technology of the past several years, the channel length of FET devices has become very small, e.g., 20 nm or less, and further reductions of the channel length are desired and perhaps anticipated, e.g., channel lengths of approximately 10 nm or less are anticipated in future device generations.
"In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
"With respect to either a FET or a FinFET, threshold voltage is an important characteristic of a transistor. Simplistically, a transistor can be viewed as a simple ON-OFF switch. The threshold voltage of a transistor is the voltage level above which the transistor is turned 'ON' and becomes conductive. That is, if the voltage applied to the gate electrode of the transistor is less than the threshold voltage of the transistor, then there is no current flow through the channel region of the device (ignoring undesirable leakage currents, which are relatively small). However, when the voltage applied to the gate electrode exceeds the threshold voltage, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
"There are many situations where it would be desirable to have the ability to produce transistor devices with different threshold voltages. For example, low threshold voltage levels are desirable in devices in the critical path of a circuit because such devices must operate at very high speeds and they need to be able to drive a lot of current. As another example, it is desirable that the devices used to make an
"Various techniques have been employed in attempts to vary or control the threshold voltages of transistor devices. One technique involves introducing different dopant levels into the channel regions of different transistors in an effort to produce devices having different threshold voltages. However, given the very small channel length on current and future device generations, e.g., 10 nm gate length, it is very difficult to uniformly dope such a small area of the substrate due to inherent variations in the ion implanting process that are typically performed to introduce such dopant materials. As a result of lack of uniformity in the channel doping, this technique has resulted in devices having reduced performance capability and/or undesirable or unacceptable variations in the threshold voltage of such devices as compared to desired or target threshold voltages of such devices.
"Another technique for manufacturing devices having different threshold voltage levels involves including so-called work-function adjusting metals, such as lanthanum, aluminum and the like, as part of the gate structures of various devices, i.e., N-channel transistors and P-channel transistors, respectively. However, as the gate length of the transistors has decreased, it has become increasingly more challenging to effectively and efficiently incorporate such additional materials into the gate structure. Even if there is sufficient room for such additional work-function adjusting materials, the fabrication of such devices is extremely complex and time consuming.
"The present disclosure is directed to various methods of forming FinFET devices that may solve or at least reduce one or more of the problems identified above."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
"Generally, the present disclosure is directed to a FinFET device with a gate electrode comprised of graphene and various methods of forming such FinFET devices. One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin and, an insulating material formed on the gate electrode.
"One illustrative method disclosed herein involves forming at least one fin in a semiconducting substrate, forming a layer of gate insulation material adjacent the fin, forming a gate electrode comprised of graphene, wherein at least the layer of gate insulation material is positioned between the gate electrode and the fin, and forming an insulating material on the gate electrode. In some embodiments, the step of forming the layer of gate insulation material is performed prior to the step of forming the gate electrode, while, in other embodiments, the step of forming the layer of gate insulation material is performed after the step of forming the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
"The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
"FIGS. 1A-1F depict one illustrative method disclosed herein of forming a FinFET device with a gate electrode comprised of graphene;
"FIGS. 2A-2F depict another illustrative method disclosed herein of forming a FinFET device with a gate electrode comprised of graphene; and
"FIGS. 3A-3L depict yet another illustrative method disclosed herein of forming a FinFET device with a gate electrode comprised of graphene.
"While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims."
URL and more information on this patent application, see: Krivokapic,
Keywords for this news article include: Electronics, Semiconductor,
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