The assignee for this patent, patent number 8635578, is
Reporters obtained the following quote from the background information supplied by the inventors: "Power consumption is a major consideration in integrated circuit (IC) design. In the case of a flip-flop (FF), more power is consumed when the FF is in an enabled state. Since FFs need to transfer data from one to the other it is desirable that a second FF be enabled only when a first FF is configured to transfer data.
"It would therefore be advantageous to provide a solution ensuring that a FF is enabled only when data is being transferred to it. It would be further beneficial if such solution be further scalable to large circuit designs."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "A method implemented in a programmable system provides for power reduction of an integrated circuit design. The method is performed by a data processing system (e.g., a programmable general-purpose computer system or a computer-aided design (CAD) system) that contains a processing unit and memory storing the program instructions executed by the processing unit and a description of a design of the integrated circuit. Thus, the method may be embodied in a tangible computer software product containing program instructions that when executed on a computer in conjunction with a received circuit description perform the method.
"The method begins by receiving from storage a description of the integrated circuit or some portion thereof. For each flip-flop in the circuit the system determines at least one of a stability condition (STC) and observability don't care condition (ODC). An enable condition of the flip-flop may then be strengthened in an updated circuit design by adding an ODC controller, STC controller, or both. The ODC controller generates an enable signal to the flip-flop if an ODC check has not passed, and otherwise generates an enable signal that is an AND function of an original enable signal and of an ODC at the immediately previous clocked time unit. The STC controller generates an enable signal to the flip-flop if an STC check has not passed, and otherwise generates an enable signal that is an AND function of the original enable signal and of an STC at an immediately subsequent clocked time unit. After performing computations to compare power consumption of the updated circuit design with that of the existing design, the updated design is stored if power savings exceed a predetermined threshold, but otherwise discarded."
For more information, see this patent: Rahim, Solaiman; Movahed-Ezazi,
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