The patent's assignee for patent number 8633741 is
News editors obtained the following quote from the background information supplied by the inventors: "Reset generators are used to apply a reset signal to processors and other circuits. Such a signal may be provided shortly after a circuit has powered up so as to ensure that it is in a known state. They may also be used to supply a reset signal in the event of power supply 'brown out' or if a processor gets 'hung' or otherwise stalled such that it is probable that its operation has become compromised.
"It is well recognised that an important aspect of the 'reset' function is to avoid giving false reset signals to the processor. As a result the reset generator is generally designed to be robust in the presence of noisy supplies.
"A particularly difficult case is the state or evolution of the reset signal itself on initial power up of the reset circuit, especially when this coincides with device power up."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to a first aspect of the present invention there is provided a reset circuit comprising: a depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the depletion mode device into a high impedance state after a first predetermined period.
"It is thus possible, by use of a depletion mode device, to provide a reset circuit in which a low impedance path is immediately established between a reset voltage source and a reset terminal even during power up of the reset generator itself.
"In an exemplary embodiment of the invention the reset signal is an active low signal. Consequently the first terminal of the depletion mode device, which may be a transistor, is preferably coupled to a local ground. Advantageously the first terminal of the transistor is a source terminal and the second terminal of the transistor is a drain terminal.
"Advantageously the control circuit includes a drive arrangement connected to a gate of the transistor such that a drive signal is applied to the transistor to force it into a more conducting state prior to the end of the first predetermined period, and then to switch the transistor into a non-conducting state after the end of the first predetermined period. Advantageously the duration of the first predetermined period may be set by a timer, such as a resistor-capacitor timer. Such a timer may be implemented as a mono-stable.
"Advantageously a bias arrangement, such as a resistor connected to a supply rail, is provided to bias the reset signal to an inactive state when the transistor is not conducting.
"According to a second aspect of the present invention there is provided an electrical device having a processor or other computing element in combination with a reset circuit constituting an embodiment of the first aspect of the present invention."
For additional information on this patent, see: Spalding, Jr.,
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