Researchers Submit Patent Application, "Power Napping Technique for Accelerated Negative Bias Temperature Instability (Nbti) And/Or Positive Bias Temperature Instability (Pbti) Recovery", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "Threshold voltage (Vt) increase in metal oxide semiconductor field effect transistors (MOSFETs) due to Bias Temperature Instability (BTI) is a significant reliability concern in high-K (high dielectric constant) metal gate complementary metal oxide semiconductor (CMOS) technologies. P-type metal oxide semiconductor devices (PMOS) are affected by Negative BTI (NBTI) and n-type metal oxide semiconductor devices (NMOS) are affected by Positive BTI (PBTI). NBTI leads to PMOS Vt degradation and PBTI leads to NMOS Vt degradation.
"NBTI and PBTI increase the magnitude of the threshold-voltage of PMOS and NMOS transistors with use. Increase in threshold voltage results in reduced current, thereby causing performance degradation and reduced robustness/reliability. Several methods to characterize and sense the threshold voltage shifts exist. Circuit techniques such as power gating, dynamic voltage scaling, workload migration, and the like are used to target power and temperature challenges, and are expected to be beneficial for NBTI/PBTI as well."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Principles of the invention provide a power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery. In one aspect, an exemplary method includes operating a logic circuit in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; determining that at least a portion of the logic circuit has experienced degradation due to bias temperature instability; and, responsive to the determining, operating the logic circuit in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency.
"In another aspect, an exemplary logic circuit for operation with a supply voltage, a ground, and a plurality of primary inputs includes a circuit portion; a supply rail of the circuit portion; a ground rail of the circuit portion; and a switching arrangement. The switching arrangement is configured to interconnect the supply voltage with the supply rail of the logic circuit in a normal mode; interconnect the ground with the ground rail in the normal mode; interconnect the supply voltage with the ground rail of the logic circuit in a power napping mode; and interconnect the ground with the supply rail in the power napping mode.
"In still another aspect, design structures directed to circuits of the kind described and/or portions thereof are provided.
"As used herein, 'facilitating' an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by instructions executing on a remote processor, by sending appropriate data or commands to cause or aid the action to be performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
"One or more embodiments of the present invention may be realized in the form of an integrated circuit.
"These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 shows an exemplary circuit during normal operation and during power gating;
"FIG. 2 shows the circuit of FIG. 1 during power napping, in accordance with an aspect of the invention;
"FIG. 3 shows signal propagation through an inverter chain during power napping;
"FIG. 4 shows how recovery changes with voltage;
"FIG. 5 shows the amount of recovery in the inverter chain from power napping;
"FIGS. 6-8 show signal propagation through a random circuit during power napping;
"FIG. 9 is a flow chart for an exemplary power napping technique, according to an aspect of the invention;
"FIG. 10 shows exemplary circuit techniques to implement power supply and ground rail swapping, as well as toggling the primary inputs, during power napping mode, according to an aspect of the invention;
"FIG. 11 depicts a computer system that may be useful in implementing one or more aspects and/or elements of the invention;
"FIG. 12 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test; and
"FIG. 13 shows on-chip bias temperature instability monitoring and migration of processing to a stand-by core during power napping, according to an aspect of the invention."
For additional information on this patent application, see: Bansal, Aditya; Kim, Jae-Joon. Power Napping Technique for Accelerated Negative Bias Temperature Instability (Nbti) And/Or Positive Bias Temperature Instability (Pbti) Recovery. Filed
Keywords for this news article include: Electronics, Semiconductor,
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