This patent application is assigned to Research & Business Foundation SUNGKYUNKWAN UNIVERSITY.
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a method and apparatus for controlling writing data, and more particularly, to a method for controlling writing of data in a storage unit based on a NAND flash memory, and an apparatus thereof.
"However, in SSDs based on NAND flash memory, the performance of random write operations is not ideal. The bandwidth for a random write operation is more than ten times that required for a sequential write operation, even in current SSDs. Accordingly, a throughput of a random write operation is significantly less than a throughput of the sequential write operation. Erase operations with respect to a block from a random write operation may occur more frequently as compared with erase operations with respect to sequential write operations. Accordingly, the random write operation shortens NAND flash memory's lifespan. In NAND flash memory, in order to overwrite a page, an entire block including the page must be erased before the page is overwritten. A block of a NAND flash memory includes a plurality of pages (e.g., 128 pages). In particular, in NAND flash memory, write operations may be performed with respect to individual pages (e.g., 2 KB or 4 KB), while an erase operation is performed with respect to entire blocks (e.g., 64 or 128 pages). Accordingly, a block erase requires more time than a page write. The number of times a block can be erased is limited in the NAND flash memory. For example, the block erase number of a Single-Level Cell (SLC) is less than or equal to 100,000, the block erase number of a Multi-level Cell (MLC) is less than or equal to 10,000, and the block erase number of a Triple Level Cell (TLC) is less than or equal to 1,000. If a block is erased more times than the corresponding number, reliability of data stored in the block cannot be guaranteed. Particularly, as capacities of SSDs increase due to improvements of integration of the NAND flash memory, the number of erase operations that can be performed rapidly decreases.
"A storage unit based on NAND flash memory has a firmware called Flash Translation Layer (FTL) in consideration of a unique characteristic of the NAND flash memory. The FTL converts a Logical Block Address (LBA) requested from a file system (an element of OS) that is an upper layer of the FTL into a Physical Page Address (PPA) and performs computations such as read and write operations. Further, FTL stores and manages a conversion table for converting a logic block address and a physical page address. The FTL also controls allocation with respect to the physical page address to increase duration of the storage unit, by ensuring that specific cells of the NAND flash memory are not rapidly eroded, but that entire cells are uniformly eroded instead. Such a function is referred to as wear-leveling. Random write operations generate internal fragmentation between logic blocks addresses and physical page addresses. That is, when the random write operations are generated, a physical page may be invalidated, and garbage collection for recycling invalidated physical pages may rapidly increase. Accordingly, each time a random write operation is requested (e.g., an application program requests an Operating System (OS) to perform a write operation), the number of block erase operations with respect to the NAND flash memory increases, which reduces a performance and a duration of the NAND flash memory.
"Several methods for addressing performance and duration reduction occurring due to random writes in a storage unit based on the NAND flash memory are described as follows.
"One such method extends an over-provisioning space in the NAND flash memory. An idle memory space that a user cannot use in a NAND flash memory is referred to as an over-provisioned space. If the over-provisioning space is large, even when a random write is generated, the chance of internal fragmentation may be reduced to improve the performance and the duration. In general, 5-25% of memory capacity is used as an idle memory space. However, this method increases hardware costs.
"Another method minutely maps addresses. In this method, mapping between the logic block address and the physical page address is minutely performed. Through this method, the internal fragmentation may be reduced and the performance and duration reduction according to the random write operation may be reduced. Hybrid mapping of mapping a data block for each block and a log block for each page is more efficient than performing block unit mapping for each block. Meanwhile, page mapping the data block and the log block are more efficient. However, as the mapping units decrease in size, a capacity of a memory (e.g., Static RAM (SRAM)) in a storage unit for storing a mapping table must be increased, which disadvantageously increases hardware costs.
"Another optimization method uses a logic block address. The FTL provides various methods for optimizing using a logic block address requested from a file system. For example, an optimizing method is used to optimize an update frequency according to logic address blocks. Although the current optimization method is efficient when requesting an update in the same logic block address while updating a file block, the same method inefficient when allocating another logic block address while updating a file block."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present invention has been made to address the above-described problems and provide at least the advantages described below. An aspect of the present invention provides a method of controlling writing for improving a performance of a slow random write and a duration thereof which is an important problem of a storage unit based on a NAND flash memory, and an apparatus thereof.
"In accordance with an aspect of the present invention, a method of controlling writing data in a storage unit based on a NAND flash memory, is provided. The method includes determining reference values for classifying dirty pages to be written in the storage unit into a plurality of groups; calculating, with respect to each of the dirty pages, a hotness indicating a possibility of a change of data; classifying the dirty pages into the groups corresponding to reference values most similar to the calculated hotness; determining whether sizes of the groups are greater than a size of a segment, where the segment is a unit for performing a write request in the storage unit; and requesting a write operation for each segment with respect to groups having a size at least equal to the size of the segment to the storage unit.
"In accordance with another aspect of the present invention, an apparatus of controlling writing data is provided. The apparatus includes a storage unit including a NAND flash memory; and a controller for controlling writing of the data in the storage unit, the controller for determining reference values for classifying dirty pages to be written in the storage unit into a plurality of groups, calculating, with respect to each of the dirty pages, a hotness indicating a possibility of a change of data, classifying the dirty pages into the groups corresponding to reference values most similar to the calculated hotness, determining whether sizes of the groups are greater than a size of a segment, where the segment is a unit for performing a write request in the storage unit, and requesting a write operation for each segment with respect to groups having a size at least equal to the size of the segment to the storage unit.
BRIEF DESCRIPTION OF THE DRAWINGS
"The objects, features and advantages of the present invention will be more apparent from the following detailed description in conjunction with the accompanying drawings, in which:
"FIG. 1 is a histogram illustrating throughput of a random write operation according to a requested size according to an embodiment of the present invention;
"FIG. 2 is a block diagram illustrating a configuration of an apparatus according to an embodiment of the present invention;
"FIG. 3 is a flowchart illustrating a write operation in an apparatus including a storage unit based a NAND flash memory according to an embodiment of the present invention;
"FIG. 4 is a flowchart illustrating an iterative segment quantization method according to an embodiment of the present invention;
"FIG. 5 is a histogram illustrating an example of segment quantization according to an embodiment of the present invention;
"FIG. 6 is a flowchart illustrating segment cleaning according to an embodiment of the present invention; and
"FIGS. 7 and 8 are diagrams illustrating experimental results of a file system and another file system according to an embodiment of the present invention."
URL and more information on this patent application, see: MIN, Changwoo; CHO,
Keywords for this news article include: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY.
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