News Column

Researchers Submit Patent Application, "Processing Unit Power Management", for Approval

January 30, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor KALAGA, Srinivas (Middlesex, GB), filed on July 5, 2013, was made available online on January 16, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Many processing units, such as central processing units (CPUs), are capable of operating at different power or performance levels. At high power levels, the performance of the CPU is increased, however the power consumed by the CPU also increases. Conversely, at low power levels the power consumed by the CPU decreases, however the performance also decreases.

"In many applications, in particular where the CPU is provided in a mobile device such as a smartphone, PDA, tablet computer or laptop, it is important to achieve the right balance between performance and power consumption. Effective power management, i.e. achieving the right balance, can prolong the battery life of the device while maintaining adequate performance. The power consumed by a CPU may be varied by altering the operating voltage and/or operating frequency of the CPU.

"A known method of power management for a CPU in the prior art is to periodically sample the software load by reading the process queue length of the operating system running on the CPU. The queue length is a measure of the number of processes that are waiting to be executed by the CPU. In such known methods, when the queue length is high, the CPU power is increased, and conversely when the queue length is low, the CPU power is decreased.

"It is an object of the present invention to provide an improved method of power management for a processing unit."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "In accordance with at least one embodiment of the invention, methods, devices, systems and software are provided for supporting or implementing functionality to provide power management for a processing unit.

"According to a first aspect of the invention there is provided a method of power management for a processing unit, the processing unit configured to operate in a plurality of operating modes and further configured to provide information indicative of memory access miss events, the method comprising: receiving said information indicative of memory access miss events; determining a desired operating mode for the processing unit based at least on the received information; and causing the processing unit to operate in the desired operating mode.

"In the course of processing instructions, such as threads, certain instructions or data required by the processing unit are not stored in the lowest level cache memory. Therefore, these instructions or data would have to be retrieved from another source, such as RAM or disk storage, before the processing unit can process the instruction. While the retrieval is taking place, the processing unit idles. These events are called memory access miss events and they are indicative of the workload of the processor. Generally speaking, a relative high number of memory access miss events indicates a heavier workload of the processor,

"By using miss events, it is possible to achieve more accurate and finer grained method of controlling the operating mode of a processing unit than other known methods, such as using a measure of the length of the instructions queue (i.e. the number of outstanding instructions which are to be processed by the processing unit).

"There are different types of memory access miss events. Thus, the information indicative of memory access miss events may comprise a plurality of values, each representing a count for a different memory access miss events. As such, the method of power management in accordance with the invention may comprise calculating the first value based on a weighted average of the plurality of values. Many processing units provide information indicative of memory access miss events in the form of a counter for a given miss event, which may provide a count for an event in a given period. For example, a processing unit may provide a counter for the number of a certain type of memory access miss event in a period of 100 ms (or between 1 and 100 ms). Calculating a weighted average of these counters therefore provides an efficient method of determining a mode for the processing unit.

"In some embodiments, the processing unit may comprise a plurality of cores and may be configured to provide information indicative of memory access miss events for each of the cores. In such embodiments, the method may comprise: determining, for each of the cores, the desired operating mode based on respective first values; and causing the processing unit to operate in the desired operating mode. In a multicore processing unit, first values, which may be the weighted average of counters of memory access miss events, may be calculated for each core independently. The processing unit may be configured such that the operating mode of each of the cores is the same. Therefore out of the first values associated with each core, one is selected to determine the operating mode for the processing unit as a whole. The selected one of the first values may be associated with the processing unit operating a mode providing the highest processing throughput, and therefore the processing unit will provide sufficient performance for all concurrent tasks required of it.

"In addition, the processing unit may be configured to provide further information indicative of memory access miss events for a memory shared between at least two of the cores, and the method may comprise: determining a second value based on said further information; and causing the processing unit to operate in the desired operating mode based on a combination of the selected one of the first values and the second value.

"In some embodiments, the processing unit may have a shared memory. Therefore a second value may be calculated, in addition to the first, based on events associated with this shared memory. The operating mode may then be determined based on the first values and the second value. This may comprise calculating a sum, average or weighted average of the values. As with a multicore processing unit, the selected one of the first values may be associated with the processing unit operating a mode providing the highest processing throughput.

"Each of the plurality of modes may be associated with different power consumption and/or processing throughput of the processing unit. Furthermore, each of the plurality of modes may be associated with a different operating frequency and/or operating voltage for the processing unit.

"The information indicative of memory access miss events comprises information indicative of level 1 memory access miss events. These events can include: level 1 instruction cache misses; level 1 data cache misses; and level 1 translation lookaside buffer misses.

"The information indicative of memory access miss events may comprise information indicative of level 2 memory access miss events. These events can include: level 2 unified cache misses; and main translation lookaside buffer misses.

"The operating mode may be selected to be a relatively high power operating mode when the number of cache misses is relatively high, and the operating mode is selected to be a relatively low power operating mode when the number of cache misses is relatively low.

"The processing unit may further be configured to provide information indicative of instructions executed by the processing unit, and the method may further comprise: receiving said information indicative of instructions executed by the processing unit; and determining the desired operating mode based on both the received information indicative of memory access miss events and the received information indicative of instructions executed by the processing unit.

"According to a second aspect of the invention there is provided an apparatus for power management of a processing unit, the processing unit configured to operate in a plurality of operating modes and further configured to provide information indicative of memory access miss events, the apparatus comprising: an interface configured to receive said information indicative of memory access miss events; and a processor configured to determine a desired operating mode for the processing unit based at least on the received information, wherein the apparatus is configured to cause the processing unit to operate in the desired operating mode based on said determination. The apparatus may comprise the said processing unit.

"According to a third aspect of the invention there is provided a non-transitory computer-readable storage medium having computer readable instructions stored thereon, the computer readable instructions being executable by a computerized device to cause the computerized device to perform a method for power management for a processing unit, the processing unit configured to operate in a plurality of operating modes and further configured to provide information indicative of memory access miss events, the method comprising: receiving said information indicative of memory access miss events; determining a desired operating mode for the processing unit based at least on the received information; and causing the processing unit to operate in the desired operating mode based on said determination.

"Further features and advantages of the invention will become apparent from the following description of preferred embodiments of the invention, given by way of example only, which is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"A processing unit will now be described as an embodiment of the present invention, by way of example only, with reference to the accompanying figures in which:

"FIG. 1 is a schematic view of the processing unit of the current invention; and

"FIG. 2 is a flowchart depicting a method according to an embodiment of the invention.

"Several parts and components of the invention appear in more than one figure; for the sake of clarity the same reference numeral will be used to refer to the same part and component in all of the Figures."

For additional information on this patent application, see: KALAGA, Srinivas. Processing Unit Power Management. Filed July 5, 2013 and posted January 16, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=335&p=7&f=G&l=50&d=PG01&S1=20140109.PD.&OS=PD/20140109&RS=PD/20140109

Keywords for this news article include: Patents, Software.

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Source: Computer Weekly News


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