The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a computer-implemented method for debugging low power integrated circuit (IC) design, and in particular, to a method for creating an integrated graphic user interface to debug the IC design and provide a map of its power usage.
"Mobile and consumer electronic devices such as personal mobile computers, MP3 audio players, notebooks and digital cameras are in wide use. The drive twoards low power consumption in increasingly thinner and lighter products require integration of a number of components on an IC. For example, as more circuits are integrated on a system-on-chip (SoC) IC to perform increasingly more complex functions at lower power, the IC becomes more difficult to debug. In many low power designs, a circuit is divided into many parts, referred to as power domains, each of which may be associated with a power supply. A power domain is a collection of instances, pins and ports that can share the same power distribution network (voltage). Some of the power domains can be turned on or off by a power switch. Power switches are used to turn off unused parts of the design to conserve power consumption.
"An isolation cell is used to isolate signals between two power domains where one is switched on and one is switched off Such cells are used to isolate signals originating in a power domain that is being switched off An isolation cell ensures that when a power domain is turned off, its output has a predefined or latched value, thus leaving other active domains unaffected.
"A level shifter is typically required to change one voltage level to another voltage level across different power domains. Therefore, a low power SoC IC, in addtion to a number of digital circuits, often includes power network circuitry with a multitude of power components.
"Referring to FIG. 1, a digital circuit design is conventionally implemented in hardware description language (HDL), such as Verilog code 1. The term 'power specification' is defined herein as the description of the power intent (intended power behavior) of a circuit design. In order to implement low power network, the power description 2 specified in a power format such as Cadence Common Power Format (CPF) or Unified Power Format (UPF) is generally used to capture the power information so as to allow designers to implement low power network design in a separate file without modifying the Verilog code 1. The power format describes low power intent for design implementation, analysis and verification.
"In order to specify low power design constraints so as to minimize energy consumption, a power supply network is specified to control the distribution of power. Using UPF, one can specify the network at an abstract level. Such a network includes supply ports, supply nets, power switches, and is a high-level abstraction of the electrical network of the power aspect of the chip. Supply ports provide supply interfaces to power domains and switches, whereas supply nets connect supply ports. Since the supply network is specified apart from the logic design, the logic design specification remains independent of power supply network specifications.
"Since traditional hardware description languages (HDL) are not adequate to specify the power design information, a power format, such as UPF, provides a format without changing the existing HDL codes. For instance, UPF provides a command, create_power_domain, for creating a power domain and grouping the design instances associated with the power domain. Other power components, such as power switches, isolation cells, and level shifters may be created by using the corresponding commands defined by the power formats.
"Once the Verilog design and the power design based on the power format are taken into consideration, the IC design can be analyzed and debugged. However, to the extent that a conventional circuit design file is separate from the power network design, to debug a circuit a designer is required to establish a relationship between these two files.
"Furthermore, circuit designers are primarily focused on the functionalities of the circuit design and to creat hierarchies based on the functional and logic view of the design. However, power designers prefer to have the design hierarchies in a physical form which can be defined by a power format having a multitude of power domains within the power network design. As a result, it is inefficient and error prone for the designers to debug the entire chip if the low power network design is not viewed in the top level and does not interact with the power designer. A need continues to exist for a more efficient and reliable technique to design low power circuits."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In accordance with embodiments of the present invention, power information is displayed in a graphic window, referred to as a power map, to help users quickly understand the power structure and the relationship between power network design and circuit design to enable easy debugging. The power map includes power domains, isolation cells, level shifters, power switches and power supplies.
"One embodiment of the present invention provides a computer-implemented method for generating and displaying a power map, which is a power schematic diagram in a graphic window to show the low power network design based on the low power information defined in a power format in top level, to allow designers debug the low power network design and its associated circuit design, in which the power map comprises a plurality of power domain symbols to represent power domains and to link to the associated parts of the circuit design.
"One embodiment in the present invention is to provide a method to generate and display a power map by the following steps. First, the original circuit design HDL codes, which are some text files, are transformed into internal structure which generally is hierarchical structure called circuit design hierarchies and stored in a knowledge data base generated by a HDL parser, and the original circuit design hierarchies of the knowledge data base are regrouped to new hierarchies which are defined by power specification. In the new hierarchies, instances sharing the same power domain are grouped together. After that, the new hierarchies called power domain circuit design hierarchies are stored in a power data base. Finally, the power map is created from the power data base; it can also display the mismatches or errors between the power specification and the circuit design for those improperly handled signals that connect the power domains.
"The present invention discloses that the power map comprises low power symbols such as power domain symbols, isolation cells, level shifter cells, and power switch cells. Furthermore, the power map is used in conjunction with a simulation result to provide debugging information to the designers, such as displaying the current values of simulation result for signals in the power map at a specific simulation time or displaying the waveforms of simulation result for a period of simulation time in a waveform window by dragging and dropping selected signals in the power map into the waveform window. Moreover, the power map also provides a methodology to detect which HDL signals are not covered by isolation connection and level shifter connection, and will invoke this function automatically when power map is created.
"A feature of the power map, which is displayed in a graphic window, is that it provides some active annotation to easily communicate and interact with users. Accordingly, it is more user friendly to let users debug power network together with digital circuit design in an interactive interface.
"Another object of this invention is to provide a solution to display low power information in a graphic window with a hierarchical representation for power domains to provide an intuitive way to view the parent-child relationships among power domains.
"One embodiment in the present invention is to provide a method to generate and display the power map with a hierarchical representation, wherein the power map comprises a plurality of power domains and each of the plurality of power domains is associated with the part of the circuit design that belongs to the power domain, wherein the plurality of power domains are grouped into a plurality of sets of power domains with a representation to indicate the boundaries and parent-child relationships among the plurality of power domains. In order to present a hierarchical power map, it is necessary that at least one set of power domains contains at least two power domains in which there is a parent power domain and at least one child power domain inside the parent power domain, wherein each of the power domains is associated with a corresponding power control for controlling the power domain, and the status of the power control is displayed on the power map.
"One embodiment of the power map is generated for debugging an IC design having different operating modes, wherein the power map comprises a token to set and display current mode of the IC design. Once the current mode is changed to a new mode, the power domains of the power map will be redrawn under the new mode of the IC design as specified in the low power specification.
"The detailed technology and above preferred embodiments implemented for the present invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention.
BRIEF DESCRIPTION OF THE DRAWINGS
"The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein:
"FIG. 1 illustrates a conventional low power digital circuit design methodology;
"FIG. 2 is a flowchart of steps performed to create a power map, in accordance with one embodiment of the present invention;
"FIG. 3 illustrates a hierarchical circuit design defined by the power specification after regrouping the original circuit design hierarchy, in accordance with one embodiment of the present invention;
"FIG. 4A is a schematic diagram showing a power map, in accordance with one embodiment of the present invention;
"FIG. 4B is a schematic diagram showing an isolation rule, in accordance with one embodiment of the present invention;
"FIG. 4C is a schematic diagram showing a level shifter rule, in accordance with one embodiment of the present invention;
"FIG. 4D is a schematic diagram showing a power switch rule, in accordance with one embodiment of the present invention;
"FIG. 5 is a signal value list window, in accordance with one embodiment of the present invention;
"FIG. 6 is a waveform window, in accordance with one embodiment of the present invention;
"FIG. 7 illustrates a hierarchical representation of a power map by grouping the power domains of a circuit design according to the power control and parent-child relationships among the power domains, in accordance with one embodiment of the present invention;
"FIG. 8 is a flowchart of steps performed in creating a hierarchical representation of a power map, in accordance with one embodiment of the present invention."
For additional information on this patent application, see: Hsu, Chih-Neng; Lin, I-Liang; Feng, Wen-Chi. Hierarchical Power Map for
Keywords for this news article include: Electronics, Digital Circuits,
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