The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional Scan-BIST architectures into low power Scan-BIST architectures.
"FIG. 1 illustrates a conventional Scan-BIST architecture that a circuit 100 can be configured into during test. In the normal functional configuration, circuit 100 may be a functional sub-circuit within IC, but in test configuration it appears as shown in FIG. 1. The Scan-BIST architecture is typically realized within a sub-circuit of an IC, such as an intellectual property core DSP or CPU sub-circuit. The Scan-BIST architecture includes a generator circuit 102, compactor circuit 106, scan path circuit 104, logic circuitry to be tested 108, and controller circuit 110. Generator 102 operates to produce and output serial test stimulus patterns to scan path 104 via path 118. Compactor 106 operates to input and compress serial test response patterns from scan path 104 via path 120. Scan path 104 operates, in addition to its serial input and output modes, to output parallel test stimulus patterns to logic 108 via path 122, and input parallel response patterns from logic 108 via path 124. Controller 110 operates to produce and output the control required to operate generator 102 via path 112, scan path 104 via path 114, and compactor 106 via path 116. Generator 102 may be designed using any suitable type of circuit for producing stimulus patterns, such as linear feedback shift registers. Compactor 106 may be designed using any suitable type of circuit for compacting response patterns into signatures, such as signature analysis registers. Controller 110 may be designed using any suitable type of controller or state machine designed to autonomously operate generator 102, scan path 104, and compactor 106 during test.
"The circuit of FIG. 1 may be configured into the illustrated Scan-BIST architecture and enabled to start a test operation in response to a variety of methods, including; (1) in response to power up of the circuit, (2) in response to manipulation of external inputs to the circuit, or (3) in response to data loaded into a register, such as the IEEE 1149.1 TAP instruction register.
"FIG. 2 illustrates an example of a conventional scan cell that could be used in scan path 104. (Note: The optional scan cell multiplexer 218 and connection paths 220 and 224, shown in dotted line, will not be discussed at this time, but will be discussed later in regard to FIGS. 7 and 8.) The scan cell consists of a D-FF 204 and a multiplexer 202. During normal configuration of the circuit 100, multiplexer 202 and D-FF 204 receive control inputs SCANENA 210 and SCANCK 212 to input and output functional data to logic 108 via paths 206 and 216, respectively. In the normal configuration, the SCANCK to D-FF 204 is typically a functional clock, and the SCANENA signal is set such that the D-FF always clocks in functional data from logic 108 via path 206. During the test configuration of FIG. 2, multiplexer 202 and D-FF 204 receive control inputs SCANENA 210 and SCANCK 212 to capture test response data from logic 108 via path 206, shift data from scan input path 208 to scan output path 214, and apply test stimulus data to logic 108 via path 216. In the test configuration, the SCANCK to D-FF 204 is the test clock and the SCANENA signal is operated to allow capturing of response data from logic 108 and shifting of data from scan input 208 to scan output 214. During test configuration, SCANENA is controlled by controller 110. SCANCK may also be controlled by the controller, or it may be controlled by another source, for example the functional clock source. For the purpose of simplifying the operational description, it will be assumed that the SCANCK is controlled by the controller.
"The scan inputs 208 and scan outputs 214 of multiple scan cells are connected to form the serial scan path 104. The stimulus path 216 and response path 206 of multiple scan cells in scan path 104 form the stimulus bussing path 122 and response bussing path 124, respectively, between scan path 104 and logic 108. From this scan cell description, it is seen that the D-FF is shared between being used in the normal functional configuration and the test configuration. During scan operations through scan path 104, the stimulus outputs 216 from each scan cell ripple, since the stimulus 216 path is connected to the scan output path 214. This ripple causes all the inputs to logic 108 to actively change state during scan operations. Rippling the inputs to logic 108 causes power to be consumed by the interconnect and gating capacitance in logic 108.
"FIG. 3 illustrates a simplified example of the operation 300 of controller 110 during test. Initially the controller will be in an idle 302 or non-operational state. In response to a start test operation input, for example using one of the methods mentioned above, the controller transitions from the idle state to the operate state 304. In the operate state, the controller issues control to the generator, scan path, and compactor. In response to the control, the generator begins producing stimulus data to the scan path, the scan path begins accepting the stimulus data and outputting response data, and the compactor begins inputting and compressing the response data from the scan path. The controller remains in the operate state until the scan path has been filled with stimulus data and emptied of response data. From the operate state, the controller passes through the capture state 306 to load response data from the logic 108, then re-enters the operate state. Since the initial response data from the scan path may be unknown, unless for example the scan path is initialized at the beginning of the test, the response data input to the compactor may be delayed or masked off until after the controller has passed through the capture state 206 a first time. The process of entering the operate state to load stimulus into the scan path and empty response from the scan path, then passing through the capture state to load new response data repeats until the end of test. At end of test the controller re-enters the idle state. Upon re-entering the idle state, the controller may output an end of test (EOT) signal 111 to indicate test completion. The compactor may be designed to include an expected response signature value that is compared against the signature obtained from the test. If so, the compactor will typically output a PASS/FAIL signal 117 at end of test to indicate whether the signature taken matched the expected signature. The use of EOT and PASS/FAIL signals are assumed in subsequent Figures, but will not be shown.
"FIG. 4 illustrates a timing example of how controller 110 outputs SCANENA and SCANCK signals to scan path 104 during scan operations. In this example, a high to low transition on SCANENA, at time 406, in combination with SCANCKs occurring during time interval 402, causes stimulus data from generator 102 to be input to the scan path while response data is output to compactor 106. A low to high transition on SCANENA, at time 408, in combination with a SCANCK at time 404, causes response data from logic 108 to be loaded into the scan path. Time interval 402 relates to operate state 304 and time interval 404 relates to capture state 306 of FIG. 3. As seen in the timing and operation diagrams of FIGS. 3 and 4, the time interval sequences 404 (i.e. state 306) and 402 (i.e. state 304) cycle a sufficient number of times during test to input all stimulus to and obtain all response from logic 108.
"From the Scan-BIST architecture described in regard to FIGS. 1, 2, 3, and 4 it is seen that the stimulus 122 outputs ripple the inputs to logic 108 as data shifts through the scan path 104 during scan operations. Rippling the inputs of logic 108 causes simultaneous charging and discharging of capacitance's associated with the interconnects and gates of logic 108. For example, each scan cell stimulus output 216 to logic 108 charges and discharges a certain amount of capacitance within logic 108 at a frequency related to the data bits being scanned through the scan cell. While each scan cell stimulus output may only be directly input to a few gates within logic 108, each of the gates have outputs that fanout to inputs of other gates, and the outputs of the other gates again fanout to inputs of still further gates, and so on. Thus a transition on the stimulus output of a single scan cell may initiate hundreds of transitions within logic 108 as a result of the signal transition fanout.
"The individual power (Pi) consumed by the rippling of a given scan cell output 216 can be approximated by CV.sup.2F, where C is the capacitance being charged or discharged by the scan cell output (i.e. the capacitance of the above mentioned signal transition fanout), V is the switching voltage level, and F is the switching frequency of the scan cell output. The total power (Pt) consumed by simultaneously scanning all the scan cells in scan path 104 is approximately the sum of the individual scan cell powers, i.e. Pt=Pi.sub.1+Pi.sub.1 +. . . Pi.sub.N. The total power consumed by circuit 100 when it is configured into the Scan-BIST architecture of FIG. 1 can exceed the power consumed by circuit 100 when it is configured into its normal functional mode. This can be understood from the fact that, during normal functional mode of circuit 100, not all the D-FFs 204 simultaneously operate, as they do during scan operations occurring during the above described Scan-BIST test operation. Further, if an IC contained multiple circuits 100, the test of the IC may require testing each circuit 100 individually due to the above described test power consumption restriction. This lengthens the test time of the IC, which increased the cost to manufacture the IC. This also lengthens the powerup-self-test time of ICs in portable, battery operated systems.
"A first known method of reducing power consumption during test operation is to insert blocking circuitry, such as a gate, into the stimulus paths 216 of each scan cell, such that during scan operations the inputs to logic 108 are blocked from the effect of the scan ripple. The problem with the first method is that it adds an undesirable delay (i.e. the blocking circuit delay) in the stimulus paths 216 between D-FFs 204 and logic 108. This delay can negatively effect the performance of circuit 100 when it is configured into its normal functional mode. A second known method is to reduce the scan clock rate, such that the ripple frequency (F) is reduced. The problem with the second method is that it increases the test time since scan operations are performed at the reduced scan clock rate.
"Today, there are a number of test synthesis vendor tools that can synthesize and insert Scan-BIST architectures into ICs, similar in structure to the Scan-BIST architecture shown in FIG. 1. The use of such 'push-button' Scan-BIST insertion tools is an attractive alternative to customized Scan-BIST designs since it is an automated process. As will be described, the present disclosure provides a method of adapting these synthesized Scan-BIST architectures such that they may operate in a desired low power mode. The process of adapting Scan-BIST architectures for low power operation is also easily automated."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional Scan-BIST architectures into low power Scan-BIST architectures. The low power Scan-BIST architecture maintains the test time of Scan-BIST architectures, while requiring significantly less operational power than conventional Scan-BIST architectures. The low power Scan-BIST architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. It is also advantageous to designers of portable, battery operated systems, like wireless telephones, since ICs in the systems can be powerup-self-tested by the low power Scan-BIST architecture using only a fraction of the stored battery energy required by conventional scan-BIST architectures.
"The present disclosure described below provides a method of adapting synthesized Scan-BIST architectures to achieve a low power mode of operation. The process of adapting Scan-BIST architectures for low power operation is achieved without having to modify the above mentioned synthesized controller 110, generator 102, or compactor 106. Also, the process of adapting Scan-BIST architectures for low power operation is achieved without the aforementioned problems of; (1) having to insert blocking circuitry in the stimulus paths which adds signal delays, and (2) having to decrease the scan clock rate which increases test time.
"A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into a modified scan path, to insert scan paths A, B and C, and the insertion of an adaptor circuit in the control path 114 between controller 110 and the scan path.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
"FIG. 1 is a block diagram of a SCAN-BIST circuit having a single scan path.
"FIG. 2 is a block diagram of a scan cell.
"FIG. 3 is a flow diagram of the operation of the circuit of FIG. 1.
"FIG. 4 is a timing diagram of the operation of the circuit of FIG. 1.
"FIG. 5 is a block diagram of a SCAN-BIST circuit having a scan path arranged according to the present disclosure.
"FIG. 6 is a flow diagram of the operation of the circuit of FIG. 5.
"FIG. 7 is a block diagram of the adaptor of FIG. 5.
"FIG. 8 is a timing diagram for the operation of the adaptor of FIG. 7.
"FIG. 9 is a block diagram of the scan paths arranged according to the present disclosure.
"FIG. 10 is a block diagram of a SCAN-BIST circuit using a conventional parallel scan architecture.
"FIG. 11 is a flow chart for the operation of the parallel scan path of FIG. 10.
"FIG. 12 is a block diagram of a SCAN-BIST parallel scan path arranged according to the present disclosure.
"FIG. 13 is a flow chart of the operation of the circuit of FIG. 12.
"FIG. 14 is a block diagram of another SCAN-BIST parallel scan path circuit with the adaptor incorporated in the low cost controller.
"FIG. 15 is a flow chart of the operation of the circuit of FIG. 14.
"FIG. 16 is a block diagram of the circuit of FIG. 14 according to the present disclosure.
"FIG. 17 is a flow chart of the operation of the circuit of FIG. 16."
For additional information on this patent application, see: Whetsel, Lee D. Adapting Scan-Bist Architectures for Low Power Operation. Filed
Keywords for this news article include: Electronics, Digital Circuits,
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